Added :

1. Power Examples
2. eSim_Power.lib
3. Subcircuit for diac, scr, triac
4. Device model for Power Diode

14 files changed, 849 insertions, 0 deletions

diff --git a/src/SubcircuitLibrary/scr/D.lib b/src/SubcircuitLibrary/scr/D.lib
new file mode 100755
index 00000000..ef18bb50
--- /dev/null
+++ b/src/SubcircuitLibrary/scr/D.lib
@@ -0,0 +1,20 @@
+.MODEL D1N750 D(
++  Vj=.75
++  Nbvl=14.976
++  Cjo=175p
++  Rs=.25
++  Isr=1.859n
++  Eg=1.11
++  M=.5516
++  Nbv=1.6989
++  N=1
++  Tbv1=-21.277u
++  Bv=8.1
++  Fc=.5
++  Ikf=0
++  Nr=2
++  Ibv=20.245m
++  Is=880.5E-18
++  Xti=3
++  Ibvl=1.9556m
+)
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/scr/PowerDiode.lib b/src/SubcircuitLibrary/scr/PowerDiode.lib
new file mode 100644
index 00000000..a2f61dce
--- /dev/null
+++ b/src/SubcircuitLibrary/scr/PowerDiode.lib
@@ -0,0 +1,20 @@
+.MODEL PowerDiode D(
++ Vj=.75
++ Nbvl=14.976
++ Cjo=175p
++ Rs=.25
++ Isr=1.859n
++ Eg=1.11
++ M=.5516
++ Nbv=1.6989
++ N=1
++ Tbv1=-21.277u
++ bv=1800
++ Fc=.5
++ Ikf=0
++ Nr=2
++ Ibv=20.245m
++ Is=2.2E-15
++ Xti=3
++ Ibvl=1.9556m
+)
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/scr/analysis b/src/SubcircuitLibrary/scr/analysis
new file mode 100644
index 00000000..687c71ec
--- /dev/null
+++ b/src/SubcircuitLibrary/scr/analysis
@@ -0,0 +1 @@
+.tran 0e-12 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/scr/scr-cache.lib b/src/SubcircuitLibrary/scr/scr-cache.lib
new file mode 100644
index 00000000..24105a8a
--- /dev/null
+++ b/src/SubcircuitLibrary/scr/scr-cache.lib
@@ -0,0 +1,136 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# C
+#
+DEF C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ C?
+ C_????_*
+ C_????
+ SMD*_c
+ Capacitor*
+$ENDFPLIST
+DRAW
+P 2 0 1 20  -80 -30  80 -30 N
+P 2 0 1 20  -80 30  80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# CCCS
+#
+DEF CCCS F 0 40 Y Y 1 F N
+F0 "F" 0 150 50 H V C CNN
+F1 "CCCS" -200 -50 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+S -100 100 100 -100 0 1 0 N
+X + 1 -300 50 200 R 35 35 1 1 P
+X - 2 300 50 200 L 35 35 1 1 P
+X +c 3 -50 -200 100 U 35 35 1 1 P
+X -c 4 50 -200 100 U 35 35 1 1 P
+ENDDRAW
+ENDDEF
+#
+# DIODE
+#
+DEF DIODE D 0 40 N N 1 F N
+F0 "D" 0 100 40 H V C CNN
+F1 "DIODE" 0 -100 40 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ D?
+ S*
+$ENDFPLIST
+DRAW
+P 2 0 1 6  50 50  50 -50 N
+P 3 0 1 0  -50 50  50 0  -50 -50 F
+X A 1 -200 0 150 R 40 40 1 1 P
+X K 2 200 0 150 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 8 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "R" 50 50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# aswitch
+#
+DEF aswitch U 0 40 Y Y 1 F N
+F0 "U" 450 300 60 H V C CNN
+F1 "aswitch" 450 200 60 H V C CNN
+F2 "" 450 100 60 H V C CNN
+F3 "" 450 100 60 H V C CNN
+DRAW
+S 200 250 650 100 0 1 0 N
+X ~ 2 0 150 200 R 50 50 1 1 O
+X ~ 3 850 150 200 L 50 50 1 1 O
+X ~ 1_IN 450 -100 200 U 50 20 1 1 I
+ENDDRAW
+ENDDEF
+#
+# dc
+#
+DEF dc v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "dc" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/scr/scr.bak b/src/SubcircuitLibrary/scr/scr.bak
new file mode 100644
index 00000000..58b985d9
--- /dev/null
+++ b/src/SubcircuitLibrary/scr/scr.bak
@@ -0,0 +1,243 @@
+EESchema Schematic File Version 2
+LIBS:analogSpice
+LIBS:analogXSpice
+LIBS:convergenceAidSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:digitalXSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:scr-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "21 aug 2014"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Wire Wire Line
+	3600 3250 3600 3150
+Connection ~ 5550 4950
+Wire Wire Line
+	5800 3900 5800 3850
+Wire Wire Line
+	5800 3850 6150 3850
+Wire Wire Line
+	6150 3850 6150 4950
+Wire Wire Line
+	6150 4950 3600 4950
+Connection ~ 4300 4950
+Wire Wire Line
+	4300 4950 4300 4050
+Wire Wire Line
+	4300 4050 3850 4050
+Wire Wire Line
+	4700 5950 4700 5450
+Wire Wire Line
+	4250 5950 4250 5500
+Connection ~ 4250 4950
+Wire Wire Line
+	4250 5000 4250 4950
+Wire Wire Line
+	5550 3600 5550 3450
+Wire Wire Line
+	5550 4950 5550 4250
+Wire Wire Line
+	3600 4950 3600 4400
+Wire Wire Line
+	3600 2650 3600 2300
+Wire Wire Line
+	3600 2300 3150 2300
+Wire Wire Line
+	3600 4150 3600 4300
+Wire Wire Line
+	5550 4150 5550 4000
+Wire Wire Line
+	5550 2550 5550 2250
+Wire Wire Line
+	4700 5050 4700 4950
+Connection ~ 4700 4950
+Wire Wire Line
+	6650 2000 6650 5950
+Connection ~ 4700 5950
+Wire Wire Line
+	3850 4650 3850 5950
+Wire Wire Line
+	3850 5950 6650 5950
+Connection ~ 4250 5950
+Wire Wire Line
+	5800 4500 5800 5950
+Connection ~ 5800 5950
+$Comp
+L PORT U2
+U 3 1 53F4C93D
+P 6650 2250
+F 0 "U2" H 6650 2200 30  0000 C CNN
+F 1 "PORT" H 6650 2250 30  0000 C CNN
+F 2 "" H 6650 2250 60  0001 C CNN
+F 3 "" H 6650 2250 60  0001 C CNN
+	3    6650 2250
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U2
+U 2 1 53F4C934
+P 2900 2300
+F 0 "U2" H 2900 2250 30  0000 C CNN
+F 1 "PORT" H 2900 2300 30  0000 C CNN
+F 2 "" H 2900 2300 60  0001 C CNN
+F 3 "" H 2900 2300 60  0001 C CNN
+	2    2900 2300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U2
+U 1 1 53F4C92A
+P 6400 4950
+F 0 "U2" H 6400 4900 30  0000 C CNN
+F 1 "PORT" H 6400 4950 30  0000 C CNN
+F 2 "" H 6400 4950 60  0001 C CNN
+F 3 "" H 6400 4950 60  0001 C CNN
+	1    6400 4950
+	-1   0    0    1   
+$EndComp
+$Comp
+L CCCS F2
+U 1 1 53F4C735
+P 5750 4200
+F 0 "F2" H 5550 4300 50  0000 C CNN
+F 1 "100" H 5550 4150 50  0000 C CNN
+F 2 "" H 5750 4200 60  0001 C CNN
+F 3 "" H 5750 4200 60  0001 C CNN
+	1    5750 4200
+	0    1    1    0   
+$EndComp
+$Comp
+L DIODE D1
+U 1 1 53F4C6D9
+P 5550 3800
+F 0 "D1" H 5550 3900 40  0000 C CNN
+F 1 "D" H 5550 3700 40  0000 C CNN
+F 2 "" H 5550 3800 60  0001 C CNN
+F 3 "" H 5550 3800 60  0001 C CNN
+	1    5550 3800
+	0    1    1    0   
+$EndComp
+$Comp
+L C C1
+U 1 1 53F4C6C2
+P 4700 5250
+F 0 "C1" H 4750 5350 50  0000 L CNN
+F 1 "10u" H 4750 5150 50  0000 L CNN
+F 2 "" H 4700 5250 60  0001 C CNN
+F 3 "" H 4700 5250 60  0001 C CNN
+	1    4700 5250
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R2
+U 1 1 53F4C6BB
+P 4250 5250
+F 0 "R2" V 4330 5250 50  0000 C CNN
+F 1 "1" V 4250 5250 50  0000 C CNN
+F 2 "" H 4250 5250 60  0001 C CNN
+F 3 "" H 4250 5250 60  0001 C CNN
+	1    4250 5250
+	1    0    0    -1  
+$EndComp
+$Comp
+L CCCS F1
+U 1 1 53F4C67F
+P 3800 4350
+F 0 "F1" H 3600 4450 50  0000 C CNN
+F 1 "10" H 3600 4300 50  0000 C CNN
+F 2 "" H 3800 4350 60  0001 C CNN
+F 3 "" H 3800 4350 60  0001 C CNN
+	1    3800 4350
+	0    1    1    0   
+$EndComp
+$Comp
+L R R1
+U 1 1 53F4C5C9
+P 3600 2900
+F 0 "R1" V 3680 2900 50  0000 C CNN
+F 1 "50" V 3600 2900 50  0000 C CNN
+F 2 "" H 3600 2900 60  0001 C CNN
+F 3 "" H 3600 2900 60  0001 C CNN
+	1    3600 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L dc v1
+U 1 1 565DBF58
+P 3600 3700
+F 0 "v1" H 3400 3800 60  0000 C CNN
+F 1 "dc" H 3400 3650 60  0000 C CNN
+F 2 "R1" H 3300 3700 60  0000 C CNN
+F 3 "" H 3600 3700 60  0000 C CNN
+	1    3600 3700
+	1    0    0    -1  
+$EndComp
+$Comp
+L dc v2
+U 1 1 565DC066
+P 5550 3000
+F 0 "v2" H 5350 3100 60  0000 C CNN
+F 1 "dc" H 5350 2950 60  0000 C CNN
+F 2 "R1" H 5250 3000 60  0000 C CNN
+F 3 "" H 5550 3000 60  0000 C CNN
+	1    5550 3000
+	1    0    0    -1  
+$EndComp
+$Comp
+L aswitch U1
+U 1 1 565DC87E
+P 6400 2100
+F 0 "U1" H 6850 2400 60  0000 C CNN
+F 1 "aswitch" H 6850 2300 60  0000 C CNN
+F 2 "" H 6850 2200 60  0000 C CNN
+F 3 "" H 6850 2200 60  0000 C CNN
+	1    6400 2100
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	5950 2000 6650 2000
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/scr/scr.cir b/src/SubcircuitLibrary/scr/scr.cir
new file mode 100644
index 00000000..4b279764
--- /dev/null
+++ b/src/SubcircuitLibrary/scr/scr.cir
@@ -0,0 +1,20 @@
+* /opt/eSim/src/SubcircuitLibrary/scr/scr.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Dec  8 15:47:20 2015
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  3 7 1 PORT		
+F2  3 9 2 3 100		
+D1  5 2 D		
+C1  3 9 10u		
+F1  3 9 4 3 10		
+v1  8 4 dc		
+v2  6 5 dc		
+U1  9 1 6 aswitch		
+R1  7 8 50		
+R2  3 9 1		
+
+.end
diff --git a/src/SubcircuitLibrary/scr/scr.cir.ckt b/src/SubcircuitLibrary/scr/scr.cir.ckt
new file mode 100644
index 00000000..b0e218fd
--- /dev/null
+++ b/src/SubcircuitLibrary/scr/scr.cir.ckt
@@ -0,0 +1,19 @@
+* eeschema netlist version 1.1 (spice format) creation date: 08/21/14 11:07:22

+.include diode.lib

+

+u2  5 8 1 port

+* f2

+* Analog Switch analogswitch

+d1  4 2 diode

+v2  3 4 dc 0

+c1  5 6 10u

+r2  5 6 1

+* f1

+v1  9 7 dc 0

+r1  8 9 50

+Vf2 2 5 0

+f2 5 6 Vf2 100

+Vf1 7 5 0

+f1 5 6 Vf1 10

+a1 6 (1 3) u1

+.model u1 aswitch(cntl_on=0.25 cntl_off=0.1 r_on=0.0125 r_off=1000000)

diff --git a/src/SubcircuitLibrary/scr/scr.cir.out b/src/SubcircuitLibrary/scr/scr.cir.out
new file mode 100644
index 00000000..d600f25d
--- /dev/null
+++ b/src/SubcircuitLibrary/scr/scr.cir.out
@@ -0,0 +1,29 @@
+* /opt/esim/src/subcircuitlibrary/scr/scr.cir
+
+.include PowerDiode.lib
+* u2  3 7 1 port
+* f2
+d1 5 2 PowerDiode
+c1  3 9 10u
+* f1
+v1 8 4  dc 0
+v2 6 5  dc 0
+* u1  9 1 6 aswitch
+r1  7 8 50
+r2  3 9 1
+Vf2 2 3 0
+f2 3 9 Vf2 100
+Vf1 4 3 0
+f1 3 9 Vf1 10
+a1 9 (1 6)  u1
+* Schematic Name: aswitch, NgSpice Name: aswitch
+.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 ) 
+.tran 0e-12 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/scr/scr.cir.out~ b/src/SubcircuitLibrary/scr/scr.cir.out~
new file mode 100644
index 00000000..d600f25d
--- /dev/null
+++ b/src/SubcircuitLibrary/scr/scr.cir.out~
@@ -0,0 +1,29 @@
+* /opt/esim/src/subcircuitlibrary/scr/scr.cir
+
+.include PowerDiode.lib
+* u2  3 7 1 port
+* f2
+d1 5 2 PowerDiode
+c1  3 9 10u
+* f1
+v1 8 4  dc 0
+v2 6 5  dc 0
+* u1  9 1 6 aswitch
+r1  7 8 50
+r2  3 9 1
+Vf2 2 3 0
+f2 3 9 Vf2 100
+Vf1 4 3 0
+f1 3 9 Vf1 10
+a1 9 (1 6)  u1
+* Schematic Name: aswitch, NgSpice Name: aswitch
+.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 ) 
+.tran 0e-12 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/scr/scr.pro b/src/SubcircuitLibrary/scr/scr.pro
new file mode 100644
index 00000000..fc4ca966
--- /dev/null
+++ b/src/SubcircuitLibrary/scr/scr.pro
@@ -0,0 +1,44 @@
+update=Tue Dec  8 15:45:12 2015
+last_client=eeschema
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Sources
+LibName7=eSim_Subckt
+LibName8=eSim_User
+LibName9=power
+LibName10=device
+LibName11=transistors
+LibName12=conn
+LibName13=linear
+LibName14=regul
+LibName15=74xx
+LibName16=cmos4000
+LibName17=adc-dac
+LibName18=memory
+LibName19=xilinx
+LibName20=special
+LibName21=microcontrollers
+LibName22=dsp
+LibName23=microchip
+LibName24=analog_switches
+LibName25=motorola
+LibName26=texas
+LibName27=intel
+LibName28=audio
+LibName29=interface
+LibName30=digital-audio
+LibName31=philips
+LibName32=display
+LibName33=cypress
+LibName34=siliconi
+LibName35=opto
+LibName36=atmel
+LibName37=contrib
+LibName38=valves
diff --git a/src/SubcircuitLibrary/scr/scr.sch b/src/SubcircuitLibrary/scr/scr.sch
new file mode 100644
index 00000000..1f23ec65
--- /dev/null
+++ b/src/SubcircuitLibrary/scr/scr.sch
@@ -0,0 +1,241 @@
+EESchema Schematic File Version 2
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:scr-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "21 aug 2014"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Wire Wire Line
+	3600 3250 3600 3150
+Connection ~ 5550 4950
+Wire Wire Line
+	5800 3900 5800 3850
+Wire Wire Line
+	5800 3850 6150 3850
+Wire Wire Line
+	6150 3850 6150 4950
+Wire Wire Line
+	6150 4950 3600 4950
+Connection ~ 4300 4950
+Wire Wire Line
+	4300 4950 4300 4050
+Wire Wire Line
+	4300 4050 3850 4050
+Wire Wire Line
+	4700 5400 4700 5950
+Wire Wire Line
+	4250 5950 4250 5500
+Connection ~ 4250 4950
+Wire Wire Line
+	4250 4950 4250 5200
+Wire Wire Line
+	5550 3600 5550 3450
+Wire Wire Line
+	5550 4950 5550 4250
+Wire Wire Line
+	3600 4950 3600 4400
+Wire Wire Line
+	3600 2300 3600 2850
+Wire Wire Line
+	3600 2300 3150 2300
+Wire Wire Line
+	3600 4150 3600 4300
+Wire Wire Line
+	5550 4150 5550 4000
+Wire Wire Line
+	5550 2550 5550 2250
+Wire Wire Line
+	4700 4950 4700 5100
+Connection ~ 4700 4950
+Wire Wire Line
+	6650 2000 6650 5950
+Connection ~ 4700 5950
+Wire Wire Line
+	3850 4650 3850 5950
+Wire Wire Line
+	3850 5950 6650 5950
+Connection ~ 4250 5950
+Wire Wire Line
+	5800 4500 5800 5950
+Connection ~ 5800 5950
+$Comp
+L PORT U2
+U 3 1 53F4C93D
+P 6650 2250
+F 0 "U2" H 6650 2200 30  0000 C CNN
+F 1 "PORT" H 6650 2250 30  0000 C CNN
+F 2 "" H 6650 2250 60  0001 C CNN
+F 3 "" H 6650 2250 60  0001 C CNN
+	3    6650 2250
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U2
+U 2 1 53F4C934
+P 2900 2300
+F 0 "U2" H 2900 2250 30  0000 C CNN
+F 1 "PORT" H 2900 2300 30  0000 C CNN
+F 2 "" H 2900 2300 60  0001 C CNN
+F 3 "" H 2900 2300 60  0001 C CNN
+	2    2900 2300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U2
+U 1 1 53F4C92A
+P 6400 4950
+F 0 "U2" H 6400 4900 30  0000 C CNN
+F 1 "PORT" H 6400 4950 30  0000 C CNN
+F 2 "" H 6400 4950 60  0001 C CNN
+F 3 "" H 6400 4950 60  0001 C CNN
+	1    6400 4950
+	-1   0    0    1   
+$EndComp
+$Comp
+L CCCS F2
+U 1 1 53F4C735
+P 5750 4200
+F 0 "F2" H 5550 4300 50  0000 C CNN
+F 1 "100" H 5550 4150 50  0000 C CNN
+F 2 "" H 5750 4200 60  0001 C CNN
+F 3 "" H 5750 4200 60  0001 C CNN
+	1    5750 4200
+	0    1    1    0   
+$EndComp
+$Comp
+L DIODE D1
+U 1 1 53F4C6D9
+P 5550 3800
+F 0 "D1" H 5550 3900 40  0000 C CNN
+F 1 "D" H 5550 3700 40  0000 C CNN
+F 2 "" H 5550 3800 60  0001 C CNN
+F 3 "" H 5550 3800 60  0001 C CNN
+	1    5550 3800
+	0    1    1    0   
+$EndComp
+$Comp
+L C C1
+U 1 1 53F4C6C2
+P 4700 5250
+F 0 "C1" H 4750 5350 50  0000 L CNN
+F 1 "10u" H 4750 5150 50  0000 L CNN
+F 2 "" H 4700 5250 60  0001 C CNN
+F 3 "" H 4700 5250 60  0001 C CNN
+	1    4700 5250
+	1    0    0    -1  
+$EndComp
+$Comp
+L CCCS F1
+U 1 1 53F4C67F
+P 3800 4350
+F 0 "F1" H 3600 4450 50  0000 C CNN
+F 1 "10" H 3600 4300 50  0000 C CNN
+F 2 "" H 3800 4350 60  0001 C CNN
+F 3 "" H 3800 4350 60  0001 C CNN
+	1    3800 4350
+	0    1    1    0   
+$EndComp
+$Comp
+L dc v1
+U 1 1 565DBF58
+P 3600 3700
+F 0 "v1" H 3400 3800 60  0000 C CNN
+F 1 "dc" H 3400 3650 60  0000 C CNN
+F 2 "R1" H 3300 3700 60  0000 C CNN
+F 3 "" H 3600 3700 60  0000 C CNN
+	1    3600 3700
+	1    0    0    -1  
+$EndComp
+$Comp
+L dc v2
+U 1 1 565DC066
+P 5550 3000
+F 0 "v2" H 5350 3100 60  0000 C CNN
+F 1 "dc" H 5350 2950 60  0000 C CNN
+F 2 "R1" H 5250 3000 60  0000 C CNN
+F 3 "" H 5550 3000 60  0000 C CNN
+	1    5550 3000
+	1    0    0    -1  
+$EndComp
+$Comp
+L aswitch U1
+U 1 1 565DC87E
+P 6400 2100
+F 0 "U1" H 6850 2400 60  0000 C CNN
+F 1 "aswitch" H 6850 2300 60  0000 C CNN
+F 2 "" H 6850 2200 60  0000 C CNN
+F 3 "" H 6850 2200 60  0000 C CNN
+	1    6400 2100
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	5950 2000 6650 2000
+$Comp
+L R R1
+U 1 1 5666B019
+P 3550 2950
+F 0 "R1" H 3600 3080 50  0000 C CNN
+F 1 "50" H 3600 3000 50  0000 C CNN
+F 2 "" H 3600 2930 30  0000 C CNN
+F 3 "" V 3600 3000 30  0000 C CNN
+	1    3550 2950
+	0    1    1    0   
+$EndComp
+$Comp
+L R R2
+U 1 1 5666B17A
+P 4200 5300
+F 0 "R2" H 4250 5430 50  0000 C CNN
+F 1 "1" H 4250 5350 50  0000 C CNN
+F 2 "" H 4250 5280 30  0000 C CNN
+F 3 "" V 4250 5350 30  0000 C CNN
+	1    4200 5300
+	0    1    1    0   
+$EndComp
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/scr/scr.sub b/src/SubcircuitLibrary/scr/scr.sub
new file mode 100644
index 00000000..398c8921
--- /dev/null
+++ b/src/SubcircuitLibrary/scr/scr.sub
@@ -0,0 +1,23 @@
+* Subcircuit scr
+.subckt scr 3 7 1 
+* /opt/esim/src/subcircuitlibrary/scr/scr.cir
+.include PowerDiode.lib
+* f2
+d1 5 2 PowerDiode
+c1  3 9 10u
+* f1
+v1 8 4  dc 0
+v2 6 5  dc 0
+* u1  9 1 6 aswitch
+r1  7 8 50
+r2  3 9 1
+Vf2 2 3 0
+f2 3 9 Vf2 100
+Vf1 4 3 0
+f1 3 9 Vf1 10
+a1 9 (1 6)  u1
+* Schematic Name: aswitch, NgSpice Name: aswitch
+.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 )
+* Control Statements
+
+.ends scr
diff --git a/src/SubcircuitLibrary/scr/scr.sub~ b/src/SubcircuitLibrary/scr/scr.sub~
new file mode 100644
index 00000000..0fdddbf4
--- /dev/null
+++ b/src/SubcircuitLibrary/scr/scr.sub~
@@ -0,0 +1,23 @@
+* Subcircuit scr
+.subckt scr 3 7 1 
+* /opt/esim/src/subcircuitlibrary/scr/scr.cir
+.include PowerDiode.lib
+* f2
+d1 5 2 PowerDiode
+c1  3 9 10u
+* f1
+v1 8 4  dc 0
+v2 6 5  dc 0
+* u1  9 1 6 aswitch
+r1  7 8 50
+r2  3 9 1
+Vf2 2 3 0
+f2 3 9 Vf2 100
+Vf1 4 3 0
+f1 3 9 Vf1 10
+a1 9 [1 6 ] u1
+* Schematic Name: aswitch, NgSpice Name: aswitch
+.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 )
+* Control Statements
+
+.ends scr
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/scr/scr_Previous_Values.xml b/src/SubcircuitLibrary/scr/scr_Previous_Values.xml
new file mode 100644
index 00000000..8ff6e8d3
--- /dev/null
+++ b/src/SubcircuitLibrary/scr/scr_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">0</field1></v1><v2 name="Source type">dc<field1 name="Value">0</field1></v2></source><model><u1 name="type">aswitch<field1 name="Enter Log (default=TRUE)" /><field2 name="Enter Control OFF value (default=0.0)" /><field3 name="Enter OFF Resistance (default=1.0e12)" /><field4 name="Enter ON Resistance (default=1.0)" /><field5 name="Enter Control ON value(default=1.0)" /></u1></model><devicemodel><d1><field>/opt/eSim/src/deviceModelLibrary/Diode/PowerDiode.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ps</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file