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| author | rahulp13 | 2020-02-21 12:36:46 +0530 |
|---|---|---|
| committer | rahulp13 | 2020-02-21 12:36:46 +0530 |
| commit | 47d4daff2ab483c4cdfb82117ef0d25d53832214 (patch) | |
| tree | 55aefefe974f151de76c6a2dbe8df3b4c3393bbe /src/SubcircuitLibrary/full_sub/half_sub.cir.out | |
| parent | 453c2dab78f81046fcbd42034a86c4e759a0ff68 (diff) | |
| download | eSim-47d4daff2ab483c4cdfb82117ef0d25d53832214.tar.gz eSim-47d4daff2ab483c4cdfb82117ef0d25d53832214.tar.bz2 eSim-47d4daff2ab483c4cdfb82117ef0d25d53832214.zip | |
restructured eSim libraries
Diffstat (limited to 'src/SubcircuitLibrary/full_sub/half_sub.cir.out')
| -rw-r--r-- | src/SubcircuitLibrary/full_sub/half_sub.cir.out | 24 |
1 files changed, 0 insertions, 24 deletions
diff --git a/src/SubcircuitLibrary/full_sub/half_sub.cir.out b/src/SubcircuitLibrary/full_sub/half_sub.cir.out deleted file mode 100644 index 91816956..00000000 --- a/src/SubcircuitLibrary/full_sub/half_sub.cir.out +++ /dev/null @@ -1,24 +0,0 @@ -* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir - -* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor -* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter -* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port -a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3 -a2 net-_u1-pad1_ net-_u2-pad2_ u2 -a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4 -* Schematic Name: d_xor, NgSpice Name: d_xor -.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 10e-03 100e-03 0e-03 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end |