diff options
| author | rahulp13 | 2020-02-14 15:16:35 +0530 |
|---|---|---|
| committer | rahulp13 | 2020-02-14 15:16:35 +0530 |
| commit | cb55e59de7ee4383c04edfae7c39ad9ae9552b36 (patch) | |
| tree | de1b292a10e8196689bf1a208fe6fe32f4618846 /src/SubcircuitLibrary/full_sub/full_sub.cir | |
| parent | 08d4a0336550a0e610709970a0c5d366e109fe82 (diff) | |
| download | eSim-cb55e59de7ee4383c04edfae7c39ad9ae9552b36.tar.gz eSim-cb55e59de7ee4383c04edfae7c39ad9ae9552b36.tar.bz2 eSim-cb55e59de7ee4383c04edfae7c39ad9ae9552b36.zip | |
common code for Win and Linux, merged py2 changes
Diffstat (limited to 'src/SubcircuitLibrary/full_sub/full_sub.cir')
| -rw-r--r-- | src/SubcircuitLibrary/full_sub/full_sub.cir | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/src/SubcircuitLibrary/full_sub/full_sub.cir b/src/SubcircuitLibrary/full_sub/full_sub.cir index 7d6f198f..67359421 100644 --- a/src/SubcircuitLibrary/full_sub/full_sub.cir +++ b/src/SubcircuitLibrary/full_sub/full_sub.cir @@ -1,14 +1,14 @@ -* C:\esim\eSim\src\SubcircuitLibrary\full_sub\full_sub.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/07/19 10:58:59
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U3 Net-_U3-Pad1_ Net-_U3-Pad2_ Net-_U3-Pad3_ d_or
-U5 Net-_U5-Pad1_ Net-_U5-Pad2_ Net-_U5-Pad3_ Net-_U5-Pad4_ Net-_U3-Pad3_ PORT
-X1 Net-_U5-Pad1_ Net-_U5-Pad2_ Net-_X1-Pad3_ Net-_U3-Pad1_ half_sub
-X2 Net-_U5-Pad3_ Net-_X1-Pad3_ Net-_U5-Pad4_ Net-_U3-Pad2_ half_sub
-
-.end
+* C:\esim\eSim\src\SubcircuitLibrary\full_sub\full_sub.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/07/19 10:58:59 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U3-Pad1_ Net-_U3-Pad2_ Net-_U3-Pad3_ d_or +U5 Net-_U5-Pad1_ Net-_U5-Pad2_ Net-_U5-Pad3_ Net-_U5-Pad4_ Net-_U3-Pad3_ PORT +X1 Net-_U5-Pad1_ Net-_U5-Pad2_ Net-_X1-Pad3_ Net-_U3-Pad1_ half_sub +X2 Net-_U5-Pad3_ Net-_X1-Pad3_ Net-_U5-Pad4_ Net-_U3-Pad2_ half_sub + +.end |