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authorrahulp132020-02-14 15:16:35 +0530
committerrahulp132020-02-14 15:16:35 +0530
commitcb55e59de7ee4383c04edfae7c39ad9ae9552b36 (patch)
treede1b292a10e8196689bf1a208fe6fe32f4618846 /src/SubcircuitLibrary/7485/7485mod.sch
parent08d4a0336550a0e610709970a0c5d366e109fe82 (diff)
downloadeSim-cb55e59de7ee4383c04edfae7c39ad9ae9552b36.tar.gz
eSim-cb55e59de7ee4383c04edfae7c39ad9ae9552b36.tar.bz2
eSim-cb55e59de7ee4383c04edfae7c39ad9ae9552b36.zip
common code for Win and Linux, merged py2 changes
Diffstat (limited to 'src/SubcircuitLibrary/7485/7485mod.sch')
-rw-r--r--src/SubcircuitLibrary/7485/7485mod.sch2014
1 files changed, 1007 insertions, 1007 deletions
diff --git a/src/SubcircuitLibrary/7485/7485mod.sch b/src/SubcircuitLibrary/7485/7485mod.sch
index 9114b802..f7e537ad 100644
--- a/src/SubcircuitLibrary/7485/7485mod.sch
+++ b/src/SubcircuitLibrary/7485/7485mod.sch
@@ -1,1007 +1,1007 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_User
-LIBS:eSim_Subckt
-LIBS:7485-cache
-EELAYER 25 0
-EELAYER END
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+ 5 850 1550
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+Wire Wire Line
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+F 3 "" H 950 2650 60 0000 C CNN
+ 6 950 2650
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+$EndComp
+Wire Wire Line
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+L PORT U1
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+F 3 "" H 950 2850 60 0000 C CNN
+ 7 950 2850
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+$EndComp
+$Comp
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+ 8 950 3900
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+ 9 950 4100
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+F 2 "" H 1000 5100 60 0000 C CNN
+F 3 "" H 1000 5100 60 0000 C CNN
+ 10 1000 5100
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+$EndComp
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+F 2 "" H 1000 5300 60 0000 C CNN
+F 3 "" H 1000 5300 60 0000 C CNN
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+$EndComp
+$Comp
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+F 3 "" H 800 3150 60 0000 C CNN
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+ 2 800 3400
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+ 3 800 3600
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+Wire Wire Line
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+L PORT U1
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+F 2 "" H 10100 2050 60 0000 C CNN
+F 3 "" H 10100 2050 60 0000 C CNN
+ 12 10100 2050
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+F 3 "" H 10100 3950 60 0000 C CNN
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+F 3 "" H 10150 5450 60 0000 C CNN
+ 14 10150 5450
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+Text Notes 9650 2000 0 60 ~ 12
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+A=B\n
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+A0
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+A1
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+A<B
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+A=B
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+A2
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+B2
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+A3
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+B3
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+Wire Notes Line
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+Outputs
+$EndSCHEMATC
generated by cgit (git 2.34.1) at 2024-12-20 06:57:39 +0000