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| author | rahulp13 | 2020-02-21 12:36:46 +0530 |
|---|---|---|
| committer | rahulp13 | 2020-02-21 12:36:46 +0530 |
| commit | 47d4daff2ab483c4cdfb82117ef0d25d53832214 (patch) | |
| tree | 55aefefe974f151de76c6a2dbe8df3b4c3393bbe /src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sub | |
| parent | 453c2dab78f81046fcbd42034a86c4e759a0ff68 (diff) | |
| download | eSim-47d4daff2ab483c4cdfb82117ef0d25d53832214.tar.gz eSim-47d4daff2ab483c4cdfb82117ef0d25d53832214.tar.bz2 eSim-47d4daff2ab483c4cdfb82117ef0d25d53832214.zip | |
restructured eSim libraries
Diffstat (limited to 'src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sub')
| -rw-r--r-- | src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sub | 26 |
1 files changed, 0 insertions, 26 deletions
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sub b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sub deleted file mode 100644 index 0ea4496d..00000000 --- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sub +++ /dev/null @@ -1,26 +0,0 @@ -* Subcircuit Full-Adder
-.subckt Full-Adder net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
-* c:\esim\esim\src\subcircuitlibrary\full-adder\full-adder.cir
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_xor
-* u5 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_xor
-* u4 net-_u2-pad3_ net-_u1-pad3_ net-_u4-pad3_ d_and
-* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u3-pad3_ d_and
-* u6 net-_u3-pad3_ net-_u4-pad3_ net-_u1-pad5_ d_or
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u5
-a3 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u4-pad3_ u4
-a4 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u3-pad3_ u3
-a5 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u1-pad5_ u6
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends Full-Adder
\ No newline at end of file |