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| author | saurabhb17 | 2019-07-02 17:08:16 +0530 |
|---|---|---|
| committer | GitHub | 2019-07-02 17:08:16 +0530 |
| commit | 83d93769478a1805083666479d4ff83b875ba955 (patch) | |
| tree | d97a2f3543ab4e5164490495ee19f20352ecb71f /src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir.out | |
| parent | 29dc2de214a60216e62d80dfa3e5cbd998c2d6ee (diff) | |
| parent | 8c44f97b533607d057a28e029e42f001270f4fd4 (diff) | |
| download | eSim-83d93769478a1805083666479d4ff83b875ba955.tar.gz eSim-83d93769478a1805083666479d4ff83b875ba955.tar.bz2 eSim-83d93769478a1805083666479d4ff83b875ba955.zip | |
Merge pull request #115 from nilshah98/ese
Adding the work done by FSF 2019 eSim ECE Fellows
Diffstat (limited to 'src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir.out')
| -rw-r--r-- | src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir.out | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir.out b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir.out new file mode 100644 index 00000000..086d8b71 --- /dev/null +++ b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir.out @@ -0,0 +1,32 @@ +* c:\esim\esim\src\subcircuitlibrary\full-adder\full-adder.cir
+
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_xor
+* u5 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_xor
+* u4 net-_u2-pad3_ net-_u1-pad3_ net-_u4-pad3_ d_and
+* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u3-pad3_ d_and
+* u6 net-_u3-pad3_ net-_u4-pad3_ net-_u1-pad5_ d_or
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u5
+a3 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u4-pad3_ u4
+a4 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u3-pad3_ u3
+a5 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u1-pad5_ u6
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.ac lin 0 0Hz 0Hz
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
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