From b085a3df519debbc99acf4ded7e118a1690d6665 Mon Sep 17 00:00:00 2001
From: nilshah98
Date: Tue, 2 Jul 2019 16:42:20 +0530
Subject: Subcircuit added by ECE fellows 2019

---
 .../5bit-Ripple_carry_adder/Full-Adder.cir.out     | 32 ++++++++++++++++++++++
 1 file changed, 32 insertions(+)
 create mode 100644 src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir.out

(limited to 'src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir.out')

diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir.out b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir.out
new file mode 100644
index 00000000..086d8b71
--- /dev/null
+++ b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir.out
@@ -0,0 +1,32 @@
+* c:\esim\esim\src\subcircuitlibrary\full-adder\full-adder.cir
+
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_xor
+* u5  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_xor
+* u4  net-_u2-pad3_ net-_u1-pad3_ net-_u4-pad3_ d_and
+* u3  net-_u1-pad1_ net-_u1-pad2_ net-_u3-pad3_ d_and
+* u6  net-_u3-pad3_ net-_u4-pad3_ net-_u1-pad5_ d_or
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u5
+a3 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u4-pad3_ u4
+a4 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u3-pad3_ u3
+a5 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u1-pad5_ u6
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.ac lin 0 0Hz 0Hz
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
-- 
cgit