diff options
| author | nilshah98 | 2019-07-02 16:42:20 +0530 |
|---|---|---|
| committer | nilshah98 | 2019-07-02 16:46:12 +0530 |
| commit | b085a3df519debbc99acf4ded7e118a1690d6665 (patch) | |
| tree | 0fc3e5389c2a77a97d1a065875fe87ddee2c23f4 /src/SubcircuitLibrary/4025 | |
| parent | e7cd941bc4a48ff8684e4db6b9dff0efeb51fa6e (diff) | |
| download | eSim-b085a3df519debbc99acf4ded7e118a1690d6665.tar.gz eSim-b085a3df519debbc99acf4ded7e118a1690d6665.tar.bz2 eSim-b085a3df519debbc99acf4ded7e118a1690d6665.zip | |
Subcircuit added by ECE fellows 2019
Diffstat (limited to 'src/SubcircuitLibrary/4025')
| -rw-r--r-- | src/SubcircuitLibrary/4025/4025-cache.lib | 82 | ||||
| -rw-r--r-- | src/SubcircuitLibrary/4025/4025.cir | 17 | ||||
| -rw-r--r-- | src/SubcircuitLibrary/4025/4025.cir.out | 36 | ||||
| -rw-r--r-- | src/SubcircuitLibrary/4025/4025.pro | 45 | ||||
| -rw-r--r-- | src/SubcircuitLibrary/4025/4025.sch | 302 | ||||
| -rw-r--r-- | src/SubcircuitLibrary/4025/4025.sub | 30 | ||||
| -rw-r--r-- | src/SubcircuitLibrary/4025/4025_Previous_Values.xml | 1 | ||||
| -rw-r--r-- | src/SubcircuitLibrary/4025/analysis | 1 |
8 files changed, 514 insertions, 0 deletions
diff --git a/src/SubcircuitLibrary/4025/4025-cache.lib b/src/SubcircuitLibrary/4025/4025-cache.lib new file mode 100644 index 00000000..dd565db9 --- /dev/null +++ b/src/SubcircuitLibrary/4025/4025-cache.lib @@ -0,0 +1,82 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/4025/4025.cir b/src/SubcircuitLibrary/4025/4025.cir new file mode 100644 index 00000000..a2431c71 --- /dev/null +++ b/src/SubcircuitLibrary/4025/4025.cir @@ -0,0 +1,17 @@ +* C:\Users\Bhargav\eSim\src\SubcircuitLibrary\4025\4025.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 09:34:19
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or
+U6 Net-_U3-Pad3_ Net-_U1-Pad5_ Net-_U1-Pad6_ d_nor
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT
+U4 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U4-Pad3_ d_or
+U7 Net-_U4-Pad3_ Net-_U1-Pad13_ Net-_U1-Pad10_ d_nor
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or
+U5 Net-_U2-Pad3_ Net-_U1-Pad8_ Net-_U1-Pad9_ d_nor
+
+.end
diff --git a/src/SubcircuitLibrary/4025/4025.cir.out b/src/SubcircuitLibrary/4025/4025.cir.out new file mode 100644 index 00000000..b22d91a3 --- /dev/null +++ b/src/SubcircuitLibrary/4025/4025.cir.out @@ -0,0 +1,36 @@ +* c:\users\bhargav\esim\src\subcircuitlibrary\4025\4025.cir
+
+* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u6 net-_u3-pad3_ net-_u1-pad5_ net-_u1-pad6_ d_nor
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
+* u4 net-_u1-pad11_ net-_u1-pad12_ net-_u4-pad3_ d_or
+* u7 net-_u4-pad3_ net-_u1-pad13_ net-_u1-pad10_ d_nor
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u5 net-_u2-pad3_ net-_u1-pad8_ net-_u1-pad9_ d_nor
+a1 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a2 [net-_u3-pad3_ net-_u1-pad5_ ] net-_u1-pad6_ u6
+a3 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u4-pad3_ u4
+a4 [net-_u4-pad3_ net-_u1-pad13_ ] net-_u1-pad10_ u7
+a5 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a6 [net-_u2-pad3_ net-_u1-pad8_ ] net-_u1-pad9_ u5
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u5 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/4025/4025.pro b/src/SubcircuitLibrary/4025/4025.pro new file mode 100644 index 00000000..3c05588e --- /dev/null +++ b/src/SubcircuitLibrary/4025/4025.pro @@ -0,0 +1,45 @@ +update=05/31/19 09:27:16
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=power
+LibName2=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Analog
+LibName3=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Devices
+LibName4=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Digital
+LibName5=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Hybrid
+LibName6=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Miscellaneous
+LibName7=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Plot
+LibName8=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Power
+LibName9=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_PSpice
+LibName10=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Sources
+LibName11=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Subckt
+LibName12=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_User
diff --git a/src/SubcircuitLibrary/4025/4025.sch b/src/SubcircuitLibrary/4025/4025.sch new file mode 100644 index 00000000..2a0cb4bc --- /dev/null +++ b/src/SubcircuitLibrary/4025/4025.sch @@ -0,0 +1,302 @@ +EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:4025-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_or U3
+U 1 1 5CEE0A15
+P 4850 3000
+F 0 "U3" H 4850 3000 60 0000 C CNN
+F 1 "d_or" H 4850 3100 60 0000 C CNN
+F 2 "" H 4850 3000 60 0000 C CNN
+F 3 "" H 4850 3000 60 0000 C CNN
+ 1 4850 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U6
+U 1 1 5CEE0AE8
+P 6100 3050
+F 0 "U6" H 6100 3050 60 0000 C CNN
+F 1 "d_nor" H 6150 3150 60 0000 C CNN
+F 2 "" H 6100 3050 60 0000 C CNN
+F 3 "" H 6100 3050 60 0000 C CNN
+ 1 6100 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5CEE0B21
+P 3900 2900
+F 0 "U1" H 3950 3000 30 0000 C CNN
+F 1 "PORT" H 3900 2900 30 0000 C CNN
+F 2 "" H 3900 2900 60 0000 C CNN
+F 3 "" H 3900 2900 60 0000 C CNN
+ 3 3900 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5CEE0B4F
+P 3900 3150
+F 0 "U1" H 3950 3250 30 0000 C CNN
+F 1 "PORT" H 3900 3150 30 0000 C CNN
+F 2 "" H 3900 3150 60 0000 C CNN
+F 3 "" H 3900 3150 60 0000 C CNN
+ 4 3900 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 5CEE0B87
+P 5200 4450
+F 0 "U1" H 5250 4550 30 0000 C CNN
+F 1 "PORT" H 5200 4450 30 0000 C CNN
+F 2 "" H 5200 4450 60 0000 C CNN
+F 3 "" H 5200 4450 60 0000 C CNN
+ 8 5200 4450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 5CEE0BBA
+P 3900 3500
+F 0 "U1" H 3950 3600 30 0000 C CNN
+F 1 "PORT" H 3900 3500 30 0000 C CNN
+F 2 "" H 3900 3500 60 0000 C CNN
+F 3 "" H 3900 3500 60 0000 C CNN
+ 11 3900 3500
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4150 2900 4400 2900
+Wire Wire Line
+ 4150 3150 4300 3150
+Wire Wire Line
+ 4300 3150 4300 3000
+Wire Wire Line
+ 4300 3000 4400 3000
+Wire Wire Line
+ 5300 2950 5650 2950
+Wire Wire Line
+ 5500 3150 5650 3150
+Wire Wire Line
+ 5650 3150 5650 3050
+Wire Wire Line
+ 6550 3000 6750 3000
+$Comp
+L d_or U4
+U 1 1 5CEE1CD2
+P 4850 3600
+F 0 "U4" H 4850 3600 60 0000 C CNN
+F 1 "d_or" H 4850 3700 60 0000 C CNN
+F 2 "" H 4850 3600 60 0000 C CNN
+F 3 "" H 4850 3600 60 0000 C CNN
+ 1 4850 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U7
+U 1 1 5CEE1CD8
+P 6100 3650
+F 0 "U7" H 6100 3650 60 0000 C CNN
+F 1 "d_nor" H 6150 3750 60 0000 C CNN
+F 2 "" H 6100 3650 60 0000 C CNN
+F 3 "" H 6100 3650 60 0000 C CNN
+ 1 6100 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5CEE1CDE
+P 5250 3150
+F 0 "U1" H 5300 3250 30 0000 C CNN
+F 1 "PORT" H 5250 3150 30 0000 C CNN
+F 2 "" H 5250 3150 60 0000 C CNN
+F 3 "" H 5250 3150 60 0000 C CNN
+ 5 5250 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 5CEE1CE4
+P 7000 3000
+F 0 "U1" H 7050 3100 30 0000 C CNN
+F 1 "PORT" H 7000 3000 30 0000 C CNN
+F 2 "" H 7000 3000 60 0000 C CNN
+F 3 "" H 7000 3000 60 0000 C CNN
+ 6 7000 3000
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 5CEE1CEA
+P 6950 4300
+F 0 "U1" H 7000 4400 30 0000 C CNN
+F 1 "PORT" H 6950 4300 30 0000 C CNN
+F 2 "" H 6950 4300 60 0000 C CNN
+F 3 "" H 6950 4300 60 0000 C CNN
+ 9 6950 4300
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 5CEE1CF0
+P 3900 3750
+F 0 "U1" H 3950 3850 30 0000 C CNN
+F 1 "PORT" H 3900 3750 30 0000 C CNN
+F 2 "" H 3900 3750 60 0000 C CNN
+F 3 "" H 3900 3750 60 0000 C CNN
+ 12 3900 3750
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4150 3500 4400 3500
+Wire Wire Line
+ 4150 3750 4300 3750
+Wire Wire Line
+ 4300 3750 4300 3600
+Wire Wire Line
+ 4300 3600 4400 3600
+Wire Wire Line
+ 5300 3550 5650 3550
+Wire Wire Line
+ 5500 3750 5650 3750
+Wire Wire Line
+ 5650 3750 5650 3650
+Wire Wire Line
+ 6550 3600 6750 3600
+$Comp
+L d_or U2
+U 1 1 5CEE1F80
+P 4800 4300
+F 0 "U2" H 4800 4300 60 0000 C CNN
+F 1 "d_or" H 4800 4400 60 0000 C CNN
+F 2 "" H 4800 4300 60 0000 C CNN
+F 3 "" H 4800 4300 60 0000 C CNN
+ 1 4800 4300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U5
+U 1 1 5CEE1F86
+P 6050 4350
+F 0 "U5" H 6050 4350 60 0000 C CNN
+F 1 "d_nor" H 6100 4450 60 0000 C CNN
+F 2 "" H 6050 4350 60 0000 C CNN
+F 3 "" H 6050 4350 60 0000 C CNN
+ 1 6050 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5CEE1F8C
+P 3850 4200
+F 0 "U1" H 3900 4300 30 0000 C CNN
+F 1 "PORT" H 3850 4200 30 0000 C CNN
+F 2 "" H 3850 4200 60 0000 C CNN
+F 3 "" H 3850 4200 60 0000 C CNN
+ 1 3850 4200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5CEE1F92
+P 3850 4450
+F 0 "U1" H 3900 4550 30 0000 C CNN
+F 1 "PORT" H 3850 4450 30 0000 C CNN
+F 2 "" H 3850 4450 60 0000 C CNN
+F 3 "" H 3850 4450 60 0000 C CNN
+ 2 3850 4450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 5CEE1F98
+P 8450 3500
+F 0 "U1" H 8500 3600 30 0000 C CNN
+F 1 "PORT" H 8450 3500 30 0000 C CNN
+F 2 "" H 8450 3500 60 0000 C CNN
+F 3 "" H 8450 3500 60 0000 C CNN
+ 7 8450 3500
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 5CEE1F9E
+P 7000 3600
+F 0 "U1" H 7050 3700 30 0000 C CNN
+F 1 "PORT" H 7000 3600 30 0000 C CNN
+F 2 "" H 7000 3600 60 0000 C CNN
+F 3 "" H 7000 3600 60 0000 C CNN
+ 10 7000 3600
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4100 4200 4350 4200
+Wire Wire Line
+ 4100 4450 4250 4450
+Wire Wire Line
+ 4250 4450 4250 4300
+Wire Wire Line
+ 4250 4300 4350 4300
+Wire Wire Line
+ 5250 4250 5600 4250
+Wire Wire Line
+ 5450 4450 5600 4450
+Wire Wire Line
+ 5600 4450 5600 4350
+Wire Wire Line
+ 6500 4300 6700 4300
+Wire Wire Line
+ 7800 3500 8200 3500
+NoConn ~ 7800 3500
+$Comp
+L PORT U1
+U 13 1 5CEE2827
+P 5250 3750
+F 0 "U1" H 5300 3850 30 0000 C CNN
+F 1 "PORT" H 5250 3750 30 0000 C CNN
+F 2 "" H 5250 3750 60 0000 C CNN
+F 3 "" H 5250 3750 60 0000 C CNN
+ 13 5250 3750
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 7800 3850 8200 3850
+NoConn ~ 7800 3850
+$Comp
+L PORT U1
+U 14 1 5CEE289D
+P 8450 3850
+F 0 "U1" H 8500 3950 30 0000 C CNN
+F 1 "PORT" H 8450 3850 30 0000 C CNN
+F 2 "" H 8450 3850 60 0000 C CNN
+F 3 "" H 8450 3850 60 0000 C CNN
+ 14 8450 3850
+ -1 0 0 1
+$EndComp
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4025/4025.sub b/src/SubcircuitLibrary/4025/4025.sub new file mode 100644 index 00000000..867617fd --- /dev/null +++ b/src/SubcircuitLibrary/4025/4025.sub @@ -0,0 +1,30 @@ +* Subcircuit 4025
+.subckt 4025 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ?
+* c:\users\bhargav\esim\src\subcircuitlibrary\4025\4025.cir
+* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u6 net-_u3-pad3_ net-_u1-pad5_ net-_u1-pad6_ d_nor
+* u4 net-_u1-pad11_ net-_u1-pad12_ net-_u4-pad3_ d_or
+* u7 net-_u4-pad3_ net-_u1-pad13_ net-_u1-pad10_ d_nor
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u5 net-_u2-pad3_ net-_u1-pad8_ net-_u1-pad9_ d_nor
+a1 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a2 [net-_u3-pad3_ net-_u1-pad5_ ] net-_u1-pad6_ u6
+a3 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u4-pad3_ u4
+a4 [net-_u4-pad3_ net-_u1-pad13_ ] net-_u1-pad10_ u7
+a5 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a6 [net-_u2-pad3_ net-_u1-pad8_ ] net-_u1-pad9_ u5
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u5 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4025
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4025/4025_Previous_Values.xml b/src/SubcircuitLibrary/4025/4025_Previous_Values.xml new file mode 100644 index 00000000..228a19a0 --- /dev/null +++ b/src/SubcircuitLibrary/4025/4025_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u3 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u3><u6 name="type">d_nor<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u6><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4><u7 name="type">d_nor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u7><u2 name="type">d_or<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u2><u5 name="type">d_nor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u5></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4025/analysis b/src/SubcircuitLibrary/4025/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/4025/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file |