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authornilshah982019-07-02 16:42:20 +0530
committernilshah982019-07-02 16:46:12 +0530
commitb085a3df519debbc99acf4ded7e118a1690d6665 (patch)
tree0fc3e5389c2a77a97d1a065875fe87ddee2c23f4 /src/SubcircuitLibrary/2bitmul/2bitmul.cir
parente7cd941bc4a48ff8684e4db6b9dff0efeb51fa6e (diff)
downloadeSim-b085a3df519debbc99acf4ded7e118a1690d6665.tar.gz
eSim-b085a3df519debbc99acf4ded7e118a1690d6665.tar.bz2
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Subcircuit added by ECE fellows 2019
Diffstat (limited to 'src/SubcircuitLibrary/2bitmul/2bitmul.cir')
-rw-r--r--src/SubcircuitLibrary/2bitmul/2bitmul.cir17
1 files changed, 17 insertions, 0 deletions
diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.cir b/src/SubcircuitLibrary/2bitmul/2bitmul.cir
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+* C:\esim\eSim\src\SubcircuitLibrary\2bitmul\2bitmul.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/07/19 11:42:27
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U5 Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad5_ d_and
+U4 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U4-Pad3_ d_and
+U3 Net-_U1-Pad1_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_and
+U2 Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_U2-Pad3_ d_and
+X2 Net-_U4-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad6_ Net-_X1-Pad1_ half_adder
+X1 Net-_X1-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad7_ Net-_U1-Pad8_ half_adder
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ PORT
+
+.end