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authorfossee2019-09-03 10:51:06 +0530
committerfossee2019-09-03 10:51:06 +0530
commit7f369bc451dc4189529efa1e5c9febe52c68a876 (patch)
treedac91d36548334efc67ed1851e780a90ba0c9076 /nghdl/Example/xor/myxor.vhdl
parentd4c0c9f05d7b6d5246c9a193fb4c5a01e2eae213 (diff)
downloadeSim-7f369bc451dc4189529efa1e5c9febe52c68a876.tar.gz
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separated nghdl
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diff --git a/nghdl/Example/xor/myxor.vhdl b/nghdl/Example/xor/myxor.vhdl
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-library ieee;
-use ieee.std_logic_1164.all;
-
-entity myxor is
- port (a : in std_logic_vector(0 downto 0);
- b : in std_logic_vector(0 downto 0);
- c : out std_logic_vector(0 downto 0));
- end myxor;
-
- architecture rtl of myxor is
- begin
-
- c <= a xor b;
-
- end rtl;