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| author | Sumanto Kar | 2024-11-21 23:44:11 +0530 |
|---|---|---|
| committer | Sumanto Kar | 2024-11-21 23:44:11 +0530 |
| commit | a5c91e10c52b25653c372942dd7c9f438e5d1425 (patch) | |
| tree | d772ea108c41a4ac920374aac33ef4f08dfa4d9c /library | |
| parent | 74387947b07c30cccb36bb125a363e605de07440 (diff) | |
| download | eSim-a5c91e10c52b25653c372942dd7c9f438e5d1425.tar.gz eSim-a5c91e10c52b25653c372942dd7c9f438e5d1425.tar.bz2 eSim-a5c91e10c52b25653c372942dd7c9f438e5d1425.zip | |
SN74LS148 is an 8-to-3 priority encoder
Diffstat (limited to 'library')
31 files changed, 3315 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/SN74LS148_sub/3_and-cache.lib b/library/SubcircuitLibrary/SN74LS148_sub/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS148_sub/3_and.cir b/library/SubcircuitLibrary/SN74LS148_sub/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LS148_sub/3_and.cir.out b/library/SubcircuitLibrary/SN74LS148_sub/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS148_sub/3_and.pro b/library/SubcircuitLibrary/SN74LS148_sub/3_and.pro new file mode 100644 index 00000000..06813ca7 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/3_and.pro @@ -0,0 +1,43 @@ +update=Wed Mar 18 19:54:53 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_Subckt +LibName10=eSim_User diff --git a/library/SubcircuitLibrary/SN74LS148_sub/3_and.sch b/library/SubcircuitLibrary/SN74LS148_sub/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS148_sub/3_and.sub b/library/SubcircuitLibrary/SN74LS148_sub/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS148_sub/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS148_sub/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS148_sub/4_and-cache.lib b/library/SubcircuitLibrary/SN74LS148_sub/4_and-cache.lib new file mode 100644 index 00000000..60f1a83d --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS148_sub/4_and-rescue.lib b/library/SubcircuitLibrary/SN74LS148_sub/4_and-rescue.lib new file mode 100644 index 00000000..e3833051 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/4_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS148_sub/4_and.cir b/library/SubcircuitLibrary/SN74LS148_sub/4_and.cir new file mode 100644 index 00000000..fdf2e107 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LS148_sub/4_and.cir.out b/library/SubcircuitLibrary/SN74LS148_sub/4_and.cir.out new file mode 100644 index 00000000..f40e5bc6 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS148_sub/4_and.pro b/library/SubcircuitLibrary/SN74LS148_sub/4_and.pro new file mode 100644 index 00000000..b13a0a82 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/4_and.pro @@ -0,0 +1,57 @@ +update=Wed Mar 18 19:54:24 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=4_and-rescue +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/library/SubcircuitLibrary/SN74LS148_sub/4_and.sch b/library/SubcircuitLibrary/SN74LS148_sub/4_and.sch new file mode 100644 index 00000000..f5e8febd --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/4_and.sch @@ -0,0 +1,151 @@ +EESchema Schematic File Version 2 +LIBS:4_and-rescue +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-4_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +Text Notes 3450 2650 0 60 ~ 12 +in1 +Text Notes 3450 2950 0 60 ~ 12 +in2 +Text Notes 3500 3300 0 60 ~ 12 +in3 +Text Notes 3500 3550 0 60 ~ 12 +in4 +Text Notes 6150 3350 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS148_sub/4_and.sub b/library/SubcircuitLibrary/SN74LS148_sub/4_and.sub new file mode 100644 index 00000000..8663f37e --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS148_sub/4_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS148_sub/4_and_Previous_Values.xml new file mode 100644 index 00000000..f2ba0130 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/4_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS148_sub/5_and-cache.lib b/library/SubcircuitLibrary/SN74LS148_sub/5_and-cache.lib new file mode 100644 index 00000000..fc177c1f --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/5_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-5_and +# +DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS148_sub/5_and-rescue.lib b/library/SubcircuitLibrary/SN74LS148_sub/5_and-rescue.lib new file mode 100644 index 00000000..483b8efb --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/5_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-5_and +# +DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS148_sub/5_and.cir b/library/SubcircuitLibrary/SN74LS148_sub/5_and.cir new file mode 100644 index 00000000..6a05b9b5 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/5_and.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LS148_sub/5_and.cir.out b/library/SubcircuitLibrary/SN74LS148_sub/5_and.cir.out new file mode 100644 index 00000000..6a6b126a --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/5_and.cir.out @@ -0,0 +1,22 @@ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS148_sub/5_and.pro b/library/SubcircuitLibrary/SN74LS148_sub/5_and.pro new file mode 100644 index 00000000..c16a3f85 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/5_and.pro @@ -0,0 +1,49 @@ +update=Wed Mar 18 19:59:53 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=cypress +LibName2=siliconi +LibName3=opto +LibName4=atmel +LibName5=contrib +LibName6=valves +LibName7=eSim_Analog +LibName8=eSim_Devices +LibName9=eSim_Digital +LibName10=eSim_Hybrid +LibName11=eSim_Miscellaneous +LibName12=eSim_Plot +LibName13=eSim_Power +LibName14=eSim_User +LibName15=eSim_Sources +LibName16=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN74LS148_sub/5_and.sch b/library/SubcircuitLibrary/SN74LS148_sub/5_and.sch new file mode 100644 index 00000000..aef3c043 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/5_and.sch @@ -0,0 +1,171 @@ +EESchema Schematic File Version 2 +LIBS:5_and-rescue +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_User +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:5_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-5_and X1 +U 1 1 5C9A2741 +P 3800 3350 +F 0 "X1" H 4700 3650 60 0000 C CNN +F 1 "3_and" H 4750 3850 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2764 +P 4650 3400 +F 0 "U2" H 4650 3400 60 0000 C CNN +F 1 "d_and" H 4700 3500 60 0000 C CNN +F 2 "" H 4650 3400 60 0000 C CNN +F 3 "" H 4650 3400 60 0000 C CNN + 1 4650 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2791 +P 5550 3200 +F 0 "U3" H 5550 3200 60 0000 C CNN +F 1 "d_and" H 5600 3300 60 0000 C CNN +F 2 "" H 5550 3200 60 0000 C CNN +F 3 "" H 5550 3200 60 0000 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3100 5100 2950 +Wire Wire Line + 5100 3200 5100 3350 +Wire Wire Line + 4250 2850 4250 2700 +Wire Wire Line + 4250 2700 3600 2700 +Wire Wire Line + 4250 2950 4150 2950 +Wire Wire Line + 4150 2950 4150 2900 +Wire Wire Line + 4150 2900 3600 2900 +Wire Wire Line + 4200 3300 3600 3300 +Wire Wire Line + 4250 3050 4250 3100 +Wire Wire Line + 4250 3100 3600 3100 +Wire Wire Line + 4200 3400 4200 3500 +Wire Wire Line + 4200 3500 3600 3500 +Wire Wire Line + 6000 3150 6500 3150 +$Comp +L PORT U1 +U 1 1 5C9A2865 +P 3350 2700 +F 0 "U1" H 3400 2800 30 0000 C CNN +F 1 "PORT" H 3350 2700 30 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3350 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A28B6 +P 3350 2900 +F 0 "U1" H 3400 3000 30 0000 C CNN +F 1 "PORT" H 3350 2900 30 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 2 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A28D9 +P 3350 3100 +F 0 "U1" H 3400 3200 30 0000 C CNN +F 1 "PORT" H 3350 3100 30 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 3 3350 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A28FF +P 3350 3300 +F 0 "U1" H 3400 3400 30 0000 C CNN +F 1 "PORT" H 3350 3300 30 0000 C CNN +F 2 "" H 3350 3300 60 0000 C CNN +F 3 "" H 3350 3300 60 0000 C CNN + 4 3350 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2928 +P 3350 3500 +F 0 "U1" H 3400 3600 30 0000 C CNN +F 1 "PORT" H 3350 3500 30 0000 C CNN +F 2 "" H 3350 3500 60 0000 C CNN +F 3 "" H 3350 3500 60 0000 C CNN + 5 3350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A2958 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 6 6750 3150 + -1 0 0 1 +$EndComp +Text Notes 3800 2700 0 60 ~ 12 +in1 +Text Notes 3800 2900 0 60 ~ 12 +in2 +Text Notes 3800 3100 0 60 ~ 12 +in3 +Text Notes 3800 3300 0 60 ~ 12 +in4 +Text Notes 3800 3500 0 60 ~ 12 +in5 +Text Notes 6150 3150 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS148_sub/5_and.sub b/library/SubcircuitLibrary/SN74LS148_sub/5_and.sub new file mode 100644 index 00000000..35b10e17 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/5_and.sub @@ -0,0 +1,16 @@ +* Subcircuit 5_and +.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS148_sub/5_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS148_sub/5_and_Previous_Values.xml new file mode 100644 index 00000000..ae2c08a7 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/5_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC-cache.lib b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC-cache.lib new file mode 100644 index 00000000..9e35c4fc --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC-cache.lib @@ -0,0 +1,232 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# adc_bridge_8 +# +DEF adc_bridge_8 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_8" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -700 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X IN6 6 -600 -450 200 R 50 50 1 1 I +X IN7 7 -600 -550 200 R 50 50 1 1 I +X IN8 8 -600 -650 200 R 50 50 1 1 I +X OUT1 9 550 50 200 L 50 50 1 1 O +X OUT2 10 550 -50 200 L 50 50 1 1 O +X OUT3 11 550 -150 200 L 50 50 1 1 O +X OUT4 12 550 -250 200 L 50 50 1 1 O +X OUT5 13 550 -350 200 L 50 50 1 1 O +X OUT6 14 550 -450 200 L 50 50 1 1 O +X OUT7 15 550 -550 200 L 50 50 1 1 O +X OUT8 16 550 -650 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# dac_bridge_5 +# +DEF dac_bridge_5 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_5" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -400 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X OUT1 6 550 50 200 L 50 50 1 1 O +X OUT2 7 550 -50 200 L 50 50 1 1 O +X OUT3 8 550 -150 200 L 50 50 1 1 O +X OUT4 9 550 -250 200 L 50 50 1 1 O +X OUT5 10 550 -350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.cir b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.cir new file mode 100644 index 00000000..4ecebc03 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.cir @@ -0,0 +1,69 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\SN74LS148_IC\SN74LS148_IC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/26/24 23:24:07 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U23 Net-_U11-Pad2_ Net-_U2-Pad9_ Net-_U23-Pad3_ d_nand +U24 Net-_U2-Pad10_ Net-_U2-Pad11_ Net-_U24-Pad3_ d_nand +U25 Net-_U2-Pad12_ Net-_U2-Pad13_ Net-_U25-Pad3_ d_nand +U26 Net-_U2-Pad14_ Net-_U2-Pad15_ Net-_U26-Pad3_ d_nand +U29 Net-_U23-Pad3_ Net-_U23-Pad3_ Net-_U29-Pad3_ d_nand +U30 Net-_U24-Pad3_ Net-_U24-Pad3_ Net-_U30-Pad3_ d_nand +U31 Net-_U25-Pad3_ Net-_U25-Pad3_ Net-_U31-Pad3_ d_nand +U32 Net-_U26-Pad3_ Net-_U26-Pad3_ Net-_U32-Pad3_ d_nand +U41 Net-_U29-Pad3_ Net-_U30-Pad3_ Net-_U41-Pad3_ d_nand +U42 Net-_U31-Pad3_ Net-_U32-Pad3_ Net-_U42-Pad3_ d_nand +U48 Net-_U41-Pad3_ Net-_U41-Pad3_ Net-_U48-Pad3_ d_nand +U49 Net-_U42-Pad3_ Net-_U42-Pad3_ Net-_U49-Pad3_ d_nand +U50 Net-_U48-Pad3_ Net-_U49-Pad3_ Net-_U50-Pad3_ d_nand +U53 Net-_U51-Pad3_ Net-_U10-Pad2_ Net-_U52-Pad1_ d_nand +U5 Net-_U2-Pad9_ Net-_U5-Pad2_ d_inverter +X5 Net-_U5-Pad2_ Net-_U12-Pad2_ Net-_U13-Pad2_ Net-_U15-Pad2_ Net-_U10-Pad2_ Net-_U35-Pad1_ 5_and +X2 Net-_U4-Pad2_ Net-_U13-Pad2_ Net-_U15-Pad2_ Net-_U10-Pad2_ Net-_U35-Pad2_ 4_and +X1 Net-_U14-Pad1_ Net-_U15-Pad2_ Net-_U10-Pad2_ Net-_U36-Pad1_ 3_and +U16 Net-_U16-Pad1_ Net-_U10-Pad2_ Net-_U16-Pad3_ d_and +U35 Net-_U35-Pad1_ Net-_U35-Pad2_ Net-_U35-Pad3_ d_nor +U36 Net-_U36-Pad1_ Net-_U16-Pad3_ Net-_U36-Pad3_ d_nor +U43 Net-_U35-Pad3_ Net-_U35-Pad3_ Net-_U43-Pad3_ d_nor +U44 Net-_U36-Pad3_ Net-_U36-Pad3_ Net-_U44-Pad3_ d_nor +U47 Net-_U43-Pad3_ Net-_U44-Pad3_ Net-_U47-Pad3_ d_nor +X3 Net-_U12-Pad1_ Net-_U13-Pad2_ Net-_U14-Pad2_ Net-_U10-Pad2_ Net-_U27-Pad1_ 4_and +X4 Net-_U4-Pad2_ Net-_U13-Pad2_ Net-_U14-Pad2_ Net-_U10-Pad2_ Net-_U27-Pad2_ 4_and +U17 Net-_U15-Pad1_ Net-_U10-Pad2_ Net-_U17-Pad3_ d_and +U18 Net-_U16-Pad1_ Net-_U10-Pad2_ Net-_U18-Pad3_ d_and +U27 Net-_U27-Pad1_ Net-_U27-Pad2_ Net-_U27-Pad3_ d_nor +U28 Net-_U17-Pad3_ Net-_U18-Pad3_ Net-_U28-Pad3_ d_nor +U37 Net-_U27-Pad3_ Net-_U27-Pad3_ Net-_U37-Pad3_ d_nor +U38 Net-_U28-Pad3_ Net-_U28-Pad3_ Net-_U38-Pad3_ d_nor +U45 Net-_U37-Pad3_ Net-_U38-Pad3_ Net-_U45-Pad3_ d_nor +U19 Net-_U13-Pad1_ Net-_U10-Pad2_ Net-_U19-Pad3_ d_and +U20 Net-_U14-Pad1_ Net-_U10-Pad2_ Net-_U20-Pad3_ d_and +U21 Net-_U15-Pad1_ Net-_U10-Pad2_ Net-_U21-Pad3_ d_and +U22 Net-_U16-Pad1_ Net-_U10-Pad2_ Net-_U22-Pad3_ d_and +U33 Net-_U19-Pad3_ Net-_U20-Pad3_ Net-_U33-Pad3_ d_nor +U34 Net-_U21-Pad3_ Net-_U22-Pad3_ Net-_U34-Pad3_ d_nor +U39 Net-_U33-Pad3_ Net-_U33-Pad3_ Net-_U39-Pad3_ d_nor +U40 Net-_U34-Pad3_ Net-_U34-Pad3_ Net-_U40-Pad3_ d_nor +U46 Net-_U39-Pad3_ Net-_U40-Pad3_ Net-_U46-Pad3_ d_nor +U3 Net-_U2-Pad10_ Net-_U12-Pad1_ d_inverter +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter +U4 Net-_U2-Pad11_ Net-_U4-Pad2_ d_inverter +U6 Net-_U2-Pad12_ Net-_U13-Pad1_ d_inverter +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter +U7 Net-_U2-Pad13_ Net-_U14-Pad1_ d_inverter +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter +U8 Net-_U2-Pad14_ Net-_U15-Pad1_ d_inverter +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ d_inverter +U9 Net-_U2-Pad15_ Net-_U16-Pad1_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U2 Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad9_ Net-_U2-Pad10_ Net-_U2-Pad11_ Net-_U2-Pad12_ Net-_U2-Pad13_ Net-_U2-Pad14_ Net-_U2-Pad15_ Net-_U10-Pad1_ adc_bridge_8 +U11 Net-_U1-Pad9_ Net-_U11-Pad2_ adc_bridge_1 +U54 Net-_U52-Pad1_ Net-_U10-Pad2_ Net-_U52-Pad2_ d_nand +U52 Net-_U52-Pad1_ Net-_U52-Pad2_ Net-_U47-Pad3_ Net-_U45-Pad3_ Net-_U46-Pad3_ Net-_U1-Pad14_ Net-_U1-Pad13_ Net-_U1-Pad8_ Net-_U1-Pad7_ Net-_U1-Pad6_ dac_bridge_5 +U51 Net-_U50-Pad3_ Net-_U50-Pad3_ Net-_U51-Pad3_ d_nand +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.cir.out b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.cir.out new file mode 100644 index 00000000..05b10ddb --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.cir.out @@ -0,0 +1,232 @@ +* d:\fossee\esim\library\subcircuitlibrary\sn74ls148_ic\sn74ls148_ic.cir + +.include 4_and.sub +.include 5_and.sub +.include 3_and.sub +* u23 net-_u11-pad2_ net-_u2-pad9_ net-_u23-pad3_ d_nand +* u24 net-_u2-pad10_ net-_u2-pad11_ net-_u24-pad3_ d_nand +* u25 net-_u2-pad12_ net-_u2-pad13_ net-_u25-pad3_ d_nand +* u26 net-_u2-pad14_ net-_u2-pad15_ net-_u26-pad3_ d_nand +* u29 net-_u23-pad3_ net-_u23-pad3_ net-_u29-pad3_ d_nand +* u30 net-_u24-pad3_ net-_u24-pad3_ net-_u30-pad3_ d_nand +* u31 net-_u25-pad3_ net-_u25-pad3_ net-_u31-pad3_ d_nand +* u32 net-_u26-pad3_ net-_u26-pad3_ net-_u32-pad3_ d_nand +* u41 net-_u29-pad3_ net-_u30-pad3_ net-_u41-pad3_ d_nand +* u42 net-_u31-pad3_ net-_u32-pad3_ net-_u42-pad3_ d_nand +* u48 net-_u41-pad3_ net-_u41-pad3_ net-_u48-pad3_ d_nand +* u49 net-_u42-pad3_ net-_u42-pad3_ net-_u49-pad3_ d_nand +* u50 net-_u48-pad3_ net-_u49-pad3_ net-_u50-pad3_ d_nand +* u53 net-_u51-pad3_ net-_u10-pad2_ net-_u52-pad1_ d_nand +* u5 net-_u2-pad9_ net-_u5-pad2_ d_inverter +x5 net-_u5-pad2_ net-_u12-pad2_ net-_u13-pad2_ net-_u15-pad2_ net-_u10-pad2_ net-_u35-pad1_ 5_and +x2 net-_u4-pad2_ net-_u13-pad2_ net-_u15-pad2_ net-_u10-pad2_ net-_u35-pad2_ 4_and +x1 net-_u14-pad1_ net-_u15-pad2_ net-_u10-pad2_ net-_u36-pad1_ 3_and +* u16 net-_u16-pad1_ net-_u10-pad2_ net-_u16-pad3_ d_and +* u35 net-_u35-pad1_ net-_u35-pad2_ net-_u35-pad3_ d_nor +* u36 net-_u36-pad1_ net-_u16-pad3_ net-_u36-pad3_ d_nor +* u43 net-_u35-pad3_ net-_u35-pad3_ net-_u43-pad3_ d_nor +* u44 net-_u36-pad3_ net-_u36-pad3_ net-_u44-pad3_ d_nor +* u47 net-_u43-pad3_ net-_u44-pad3_ net-_u47-pad3_ d_nor +x3 net-_u12-pad1_ net-_u13-pad2_ net-_u14-pad2_ net-_u10-pad2_ net-_u27-pad1_ 4_and +x4 net-_u4-pad2_ net-_u13-pad2_ net-_u14-pad2_ net-_u10-pad2_ net-_u27-pad2_ 4_and +* u17 net-_u15-pad1_ net-_u10-pad2_ net-_u17-pad3_ d_and +* u18 net-_u16-pad1_ net-_u10-pad2_ net-_u18-pad3_ d_and +* u27 net-_u27-pad1_ net-_u27-pad2_ net-_u27-pad3_ d_nor +* u28 net-_u17-pad3_ net-_u18-pad3_ net-_u28-pad3_ d_nor +* u37 net-_u27-pad3_ net-_u27-pad3_ net-_u37-pad3_ d_nor +* u38 net-_u28-pad3_ net-_u28-pad3_ net-_u38-pad3_ d_nor +* u45 net-_u37-pad3_ net-_u38-pad3_ net-_u45-pad3_ d_nor +* u19 net-_u13-pad1_ net-_u10-pad2_ net-_u19-pad3_ d_and +* u20 net-_u14-pad1_ net-_u10-pad2_ net-_u20-pad3_ d_and +* u21 net-_u15-pad1_ net-_u10-pad2_ net-_u21-pad3_ d_and +* u22 net-_u16-pad1_ net-_u10-pad2_ net-_u22-pad3_ d_and +* u33 net-_u19-pad3_ net-_u20-pad3_ net-_u33-pad3_ d_nor +* u34 net-_u21-pad3_ net-_u22-pad3_ net-_u34-pad3_ d_nor +* u39 net-_u33-pad3_ net-_u33-pad3_ net-_u39-pad3_ d_nor +* u40 net-_u34-pad3_ net-_u34-pad3_ net-_u40-pad3_ d_nor +* u46 net-_u39-pad3_ net-_u40-pad3_ net-_u46-pad3_ d_nor +* u3 net-_u2-pad10_ net-_u12-pad1_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u4 net-_u2-pad11_ net-_u4-pad2_ d_inverter +* u6 net-_u2-pad12_ net-_u13-pad1_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u7 net-_u2-pad13_ net-_u14-pad1_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u8 net-_u2-pad14_ net-_u15-pad1_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u9 net-_u2-pad15_ net-_u16-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u2 net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u10-pad1_ adc_bridge_8 +* u11 net-_u1-pad9_ net-_u11-pad2_ adc_bridge_1 +* u54 net-_u52-pad1_ net-_u10-pad2_ net-_u52-pad2_ d_nand +* u52 net-_u52-pad1_ net-_u52-pad2_ net-_u47-pad3_ net-_u45-pad3_ net-_u46-pad3_ net-_u1-pad14_ net-_u1-pad13_ net-_u1-pad8_ net-_u1-pad7_ net-_u1-pad6_ dac_bridge_5 +* u51 net-_u50-pad3_ net-_u50-pad3_ net-_u51-pad3_ d_nand +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +a1 [net-_u11-pad2_ net-_u2-pad9_ ] net-_u23-pad3_ u23 +a2 [net-_u2-pad10_ net-_u2-pad11_ ] net-_u24-pad3_ u24 +a3 [net-_u2-pad12_ net-_u2-pad13_ ] net-_u25-pad3_ u25 +a4 [net-_u2-pad14_ net-_u2-pad15_ ] net-_u26-pad3_ u26 +a5 [net-_u23-pad3_ net-_u23-pad3_ ] net-_u29-pad3_ u29 +a6 [net-_u24-pad3_ net-_u24-pad3_ ] net-_u30-pad3_ u30 +a7 [net-_u25-pad3_ net-_u25-pad3_ ] net-_u31-pad3_ u31 +a8 [net-_u26-pad3_ net-_u26-pad3_ ] net-_u32-pad3_ u32 +a9 [net-_u29-pad3_ net-_u30-pad3_ ] net-_u41-pad3_ u41 +a10 [net-_u31-pad3_ net-_u32-pad3_ ] net-_u42-pad3_ u42 +a11 [net-_u41-pad3_ net-_u41-pad3_ ] net-_u48-pad3_ u48 +a12 [net-_u42-pad3_ net-_u42-pad3_ ] net-_u49-pad3_ u49 +a13 [net-_u48-pad3_ net-_u49-pad3_ ] net-_u50-pad3_ u50 +a14 [net-_u51-pad3_ net-_u10-pad2_ ] net-_u52-pad1_ u53 +a15 net-_u2-pad9_ net-_u5-pad2_ u5 +a16 [net-_u16-pad1_ net-_u10-pad2_ ] net-_u16-pad3_ u16 +a17 [net-_u35-pad1_ net-_u35-pad2_ ] net-_u35-pad3_ u35 +a18 [net-_u36-pad1_ net-_u16-pad3_ ] net-_u36-pad3_ u36 +a19 [net-_u35-pad3_ net-_u35-pad3_ ] net-_u43-pad3_ u43 +a20 [net-_u36-pad3_ net-_u36-pad3_ ] net-_u44-pad3_ u44 +a21 [net-_u43-pad3_ net-_u44-pad3_ ] net-_u47-pad3_ u47 +a22 [net-_u15-pad1_ net-_u10-pad2_ ] net-_u17-pad3_ u17 +a23 [net-_u16-pad1_ net-_u10-pad2_ ] net-_u18-pad3_ u18 +a24 [net-_u27-pad1_ net-_u27-pad2_ ] net-_u27-pad3_ u27 +a25 [net-_u17-pad3_ net-_u18-pad3_ ] net-_u28-pad3_ u28 +a26 [net-_u27-pad3_ net-_u27-pad3_ ] net-_u37-pad3_ u37 +a27 [net-_u28-pad3_ net-_u28-pad3_ ] net-_u38-pad3_ u38 +a28 [net-_u37-pad3_ net-_u38-pad3_ ] net-_u45-pad3_ u45 +a29 [net-_u13-pad1_ net-_u10-pad2_ ] net-_u19-pad3_ u19 +a30 [net-_u14-pad1_ net-_u10-pad2_ ] net-_u20-pad3_ u20 +a31 [net-_u15-pad1_ net-_u10-pad2_ ] net-_u21-pad3_ u21 +a32 [net-_u16-pad1_ net-_u10-pad2_ ] net-_u22-pad3_ u22 +a33 [net-_u19-pad3_ net-_u20-pad3_ ] net-_u33-pad3_ u33 +a34 [net-_u21-pad3_ net-_u22-pad3_ ] net-_u34-pad3_ u34 +a35 [net-_u33-pad3_ net-_u33-pad3_ ] net-_u39-pad3_ u39 +a36 [net-_u34-pad3_ net-_u34-pad3_ ] net-_u40-pad3_ u40 +a37 [net-_u39-pad3_ net-_u40-pad3_ ] net-_u46-pad3_ u46 +a38 net-_u2-pad10_ net-_u12-pad1_ u3 +a39 net-_u12-pad1_ net-_u12-pad2_ u12 +a40 net-_u2-pad11_ net-_u4-pad2_ u4 +a41 net-_u2-pad12_ net-_u13-pad1_ u6 +a42 net-_u13-pad1_ net-_u13-pad2_ u13 +a43 net-_u2-pad13_ net-_u14-pad1_ u7 +a44 net-_u14-pad1_ net-_u14-pad2_ u14 +a45 net-_u2-pad14_ net-_u15-pad1_ u8 +a46 net-_u15-pad1_ net-_u15-pad2_ u15 +a47 net-_u2-pad15_ net-_u16-pad1_ u9 +a48 net-_u10-pad1_ net-_u10-pad2_ u10 +a49 [net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ] [net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u10-pad1_ ] u2 +a50 [net-_u1-pad9_ ] [net-_u11-pad2_ ] u11 +a51 [net-_u52-pad1_ net-_u10-pad2_ ] net-_u52-pad2_ u54 +a52 [net-_u52-pad1_ net-_u52-pad2_ net-_u47-pad3_ net-_u45-pad3_ net-_u46-pad3_ ] [net-_u1-pad14_ net-_u1-pad13_ net-_u1-pad8_ net-_u1-pad7_ net-_u1-pad6_ ] u52 +a53 [net-_u50-pad3_ net-_u50-pad3_ ] net-_u51-pad3_ u51 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u25 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u26 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u29 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u30 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u31 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u32 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u41 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u42 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u48 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u49 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u50 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u53 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u35 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u36 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u43 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u44 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u47 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u27 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u28 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u38 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u45 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u33 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u34 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u39 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u40 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u46 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u11 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u54 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_5, NgSpice Name: dac_bridge +.model u52 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u51 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.pro b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.sch b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.sch new file mode 100644 index 00000000..f749910f --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.sch @@ -0,0 +1,1472 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN74LS148_IC-cache +EELAYER 25 0 +EELAYER END +$Descr User 31496 27559 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev 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Wire Line + 22800 10300 23800 10300 +Wire Wire Line + 23800 10300 23800 12050 +Wire Wire Line + 23800 12050 24700 12050 +Wire Wire Line + 22700 13300 23850 13300 +Wire Wire Line + 23850 13300 23850 12150 +Wire Wire Line + 23850 12150 24700 12150 +Wire Wire Line + 24700 12250 24050 12250 +Wire Wire Line + 24050 12250 24050 15450 +Wire Wire Line + 24050 15450 22750 15450 +Connection ~ 24000 7300 +Wire Wire Line + 24000 7250 24000 7350 +Wire Wire Line + 24000 7350 24050 7350 +Wire Wire Line + 24050 7250 24000 7250 +$Comp +L d_nand U51 +U 1 1 66771ED1 +P 24500 7350 +F 0 "U51" H 24500 7350 60 0000 C CNN +F 1 "d_nand" H 24550 7450 60 0000 C CNN +F 2 "" H 24500 7350 60 0000 C CNN +F 3 "" H 24500 7350 60 0000 C CNN + 1 24500 7350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 66773140 +P 6600 10800 +F 0 "U1" H 6650 10900 30 0000 C CNN +F 1 "PORT" H 6600 10800 30 0000 C CNN +F 2 "" H 6600 10800 60 0000 C CNN +F 3 "" H 6600 10800 60 0000 C CNN + 1 6600 10800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6850 10200 6850 10450 +Wire Wire Line + 6850 10450 7400 10450 +$Comp +L PORT U1 +U 2 1 66773392 +P 6250 10950 +F 0 "U1" H 6300 11050 30 0000 C CNN +F 1 "PORT" H 6250 10950 30 0000 C CNN +F 2 "" H 6250 10950 60 0000 C CNN +F 3 "" H 6250 10950 60 0000 C CNN + 2 6250 10950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6750 10400 6800 10400 +Wire Wire Line + 6800 10400 6800 10550 +Wire Wire Line + 6800 10550 7400 10550 +$Comp +L PORT U1 +U 3 1 667735C4 +P 6250 11150 +F 0 "U1" H 6300 11250 30 0000 C CNN +F 1 "PORT" H 6250 11150 30 0000 C CNN +F 2 "" H 6250 11150 60 0000 C CNN +F 3 "" H 6250 11150 60 0000 C CNN + 3 6250 11150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6700 10650 7400 10650 +$Comp +L PORT U1 +U 4 1 66773832 +P 6250 11350 +F 0 "U1" H 6300 11450 30 0000 C CNN +F 1 "PORT" H 6250 11350 30 0000 C CNN +F 2 "" H 6250 11350 60 0000 C CNN +F 3 "" H 6250 11350 60 0000 C CNN + 4 6250 11350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6850 10800 6850 10750 +Wire Wire Line + 6850 10750 7400 10750 +$Comp +L PORT U1 +U 5 1 66773B5C +P 6250 11550 +F 0 "U1" H 6300 11650 30 0000 C CNN +F 1 "PORT" H 6250 11550 30 0000 C CNN +F 2 "" H 6250 11550 60 0000 C CNN +F 3 "" H 6250 11550 60 0000 C CNN + 5 6250 11550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6500 10950 7000 10950 +Wire Wire Line + 7000 10950 7000 10850 +Wire Wire Line + 7000 10850 7400 10850 +$Comp +L PORT U1 +U 6 1 66773D97 +P 26400 12400 +F 0 "U1" H 26450 12500 30 0000 C CNN +F 1 "PORT" H 26400 12400 30 0000 C CNN +F 2 "" H 26400 12400 60 0000 C CNN +F 3 "" H 26400 12400 60 0000 C CNN + 6 26400 12400 + -1 0 0 1 +$EndComp +Wire Wire Line + 7400 10950 7100 10950 +Wire Wire Line + 7100 10950 7100 11150 +Wire Wire Line + 7100 11150 6500 11150 +$Comp +L PORT U1 +U 7 1 66773FE0 +P 26350 12200 +F 0 "U1" H 26400 12300 30 0000 C CNN +F 1 "PORT" H 26350 12200 30 0000 C CNN +F 2 "" H 26350 12200 60 0000 C CNN +F 3 "" H 26350 12200 60 0000 C CNN + 7 26350 12200 + -1 0 0 1 +$EndComp +Wire Wire Line + 6500 11350 7200 11350 +Wire Wire Line + 7200 11350 7200 11050 +Wire Wire Line + 7200 11050 7400 11050 +Wire Wire Line + 6500 11550 7350 11550 +Wire Wire Line + 7350 11550 7350 11150 +Wire Wire Line + 7350 11150 7400 11150 +Wire Wire Line + 26150 12400 26050 12400 +Wire Wire Line + 26050 12400 26050 12250 +Wire Wire Line + 26050 12250 25850 12250 +Wire Wire Line + 26100 12200 25900 12200 +Wire Wire Line + 25900 12200 25900 12150 +Wire Wire Line + 25900 12150 25850 12150 +$Comp +L PORT U1 +U 8 1 6677642A +P 26650 12050 +F 0 "U1" H 26700 12150 30 0000 C CNN +F 1 "PORT" H 26650 12050 30 0000 C CNN +F 2 "" H 26650 12050 60 0000 C CNN +F 3 "" H 26650 12050 60 0000 C CNN + 8 26650 12050 + -1 0 0 1 +$EndComp +Wire Wire Line + 26400 12050 25850 12050 +$Comp +L PORT U1 +U 9 1 66776C6A +P 13750 6250 +F 0 "U1" H 13800 6350 30 0000 C CNN +F 1 "PORT" H 13750 6250 30 0000 C CNN +F 2 "" H 13750 6250 60 0000 C CNN +F 3 "" H 13750 6250 60 0000 C CNN + 9 13750 6250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 14000 6250 14150 6250 +$Comp +L PORT U1 +U 10 1 667774D7 +P 6600 10200 +F 0 "U1" H 6650 10300 30 0000 C CNN +F 1 "PORT" H 6600 10200 30 0000 C CNN +F 2 "" H 6600 10200 60 0000 C CNN +F 3 "" H 6600 10200 60 0000 C CNN + 10 6600 10200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 6677758C +P 6500 10400 +F 0 "U1" H 6550 10500 30 0000 C CNN +F 1 "PORT" H 6500 10400 30 0000 C CNN +F 2 "" H 6500 10400 60 0000 C CNN +F 3 "" H 6500 10400 60 0000 C CNN + 11 6500 10400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 6677763D +P 6450 10650 +F 0 "U1" H 6500 10750 30 0000 C CNN +F 1 "PORT" H 6450 10650 30 0000 C CNN +F 2 "" H 6450 10650 60 0000 C CNN +F 3 "" H 6450 10650 60 0000 C CNN + 12 6450 10650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 6677815E +P 26350 11900 +F 0 "U1" H 26400 12000 30 0000 C CNN +F 1 "PORT" H 26350 11900 30 0000 C CNN +F 2 "" H 26350 11900 60 0000 C CNN +F 3 "" H 26350 11900 60 0000 C CNN + 13 26350 11900 + -1 0 0 1 +$EndComp +Wire Wire Line + 25850 11950 26100 11950 +Wire Wire Line + 26100 11950 26100 11900 +$Comp +L PORT U1 +U 14 1 667783B7 +P 26350 11650 +F 0 "U1" H 26400 11750 30 0000 C CNN +F 1 "PORT" H 26350 11650 30 0000 C CNN +F 2 "" H 26350 11650 60 0000 C CNN +F 3 "" H 26350 11650 60 0000 C CNN + 14 26350 11650 + -1 0 0 1 +$EndComp +Wire Wire Line + 26100 11650 25950 11650 +Wire Wire Line + 25950 11650 25950 11850 +Wire Wire Line + 25950 11850 25850 11850 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.sub b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.sub new file mode 100644 index 00000000..777e7e3f --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.sub @@ -0,0 +1,226 @@ +* Subcircuit SN74LS148_IC +.subckt SN74LS148_IC net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* d:\fossee\esim\library\subcircuitlibrary\sn74ls148_ic\sn74ls148_ic.cir +.include 4_and.sub +.include 5_and.sub +.include 3_and.sub +* u23 net-_u11-pad2_ net-_u2-pad9_ net-_u23-pad3_ d_nand +* u24 net-_u2-pad10_ net-_u2-pad11_ net-_u24-pad3_ d_nand +* u25 net-_u2-pad12_ net-_u2-pad13_ net-_u25-pad3_ d_nand +* u26 net-_u2-pad14_ net-_u2-pad15_ net-_u26-pad3_ d_nand +* u29 net-_u23-pad3_ net-_u23-pad3_ net-_u29-pad3_ d_nand +* u30 net-_u24-pad3_ net-_u24-pad3_ net-_u30-pad3_ d_nand +* u31 net-_u25-pad3_ net-_u25-pad3_ net-_u31-pad3_ d_nand +* u32 net-_u26-pad3_ net-_u26-pad3_ net-_u32-pad3_ d_nand +* u41 net-_u29-pad3_ net-_u30-pad3_ net-_u41-pad3_ d_nand +* u42 net-_u31-pad3_ net-_u32-pad3_ net-_u42-pad3_ d_nand +* u48 net-_u41-pad3_ net-_u41-pad3_ net-_u48-pad3_ d_nand +* u49 net-_u42-pad3_ net-_u42-pad3_ net-_u49-pad3_ d_nand +* u50 net-_u48-pad3_ net-_u49-pad3_ net-_u50-pad3_ d_nand +* u53 net-_u51-pad3_ net-_u10-pad2_ net-_u52-pad1_ d_nand +* u5 net-_u2-pad9_ net-_u5-pad2_ d_inverter +x5 net-_u5-pad2_ net-_u12-pad2_ net-_u13-pad2_ net-_u15-pad2_ net-_u10-pad2_ net-_u35-pad1_ 5_and +x2 net-_u4-pad2_ net-_u13-pad2_ net-_u15-pad2_ net-_u10-pad2_ net-_u35-pad2_ 4_and +x1 net-_u14-pad1_ net-_u15-pad2_ net-_u10-pad2_ net-_u36-pad1_ 3_and +* u16 net-_u16-pad1_ net-_u10-pad2_ net-_u16-pad3_ d_and +* u35 net-_u35-pad1_ net-_u35-pad2_ net-_u35-pad3_ d_nor +* u36 net-_u36-pad1_ net-_u16-pad3_ net-_u36-pad3_ d_nor +* u43 net-_u35-pad3_ net-_u35-pad3_ net-_u43-pad3_ d_nor +* u44 net-_u36-pad3_ net-_u36-pad3_ net-_u44-pad3_ d_nor +* u47 net-_u43-pad3_ net-_u44-pad3_ net-_u47-pad3_ d_nor +x3 net-_u12-pad1_ net-_u13-pad2_ net-_u14-pad2_ net-_u10-pad2_ net-_u27-pad1_ 4_and +x4 net-_u4-pad2_ net-_u13-pad2_ net-_u14-pad2_ net-_u10-pad2_ net-_u27-pad2_ 4_and +* u17 net-_u15-pad1_ net-_u10-pad2_ net-_u17-pad3_ d_and +* u18 net-_u16-pad1_ net-_u10-pad2_ net-_u18-pad3_ d_and +* u27 net-_u27-pad1_ net-_u27-pad2_ net-_u27-pad3_ d_nor +* u28 net-_u17-pad3_ net-_u18-pad3_ net-_u28-pad3_ d_nor +* u37 net-_u27-pad3_ net-_u27-pad3_ net-_u37-pad3_ d_nor +* u38 net-_u28-pad3_ net-_u28-pad3_ net-_u38-pad3_ d_nor +* u45 net-_u37-pad3_ net-_u38-pad3_ net-_u45-pad3_ d_nor +* u19 net-_u13-pad1_ net-_u10-pad2_ net-_u19-pad3_ d_and +* u20 net-_u14-pad1_ net-_u10-pad2_ net-_u20-pad3_ d_and +* u21 net-_u15-pad1_ net-_u10-pad2_ net-_u21-pad3_ d_and +* u22 net-_u16-pad1_ net-_u10-pad2_ net-_u22-pad3_ d_and +* u33 net-_u19-pad3_ net-_u20-pad3_ net-_u33-pad3_ d_nor +* u34 net-_u21-pad3_ net-_u22-pad3_ net-_u34-pad3_ d_nor +* u39 net-_u33-pad3_ net-_u33-pad3_ net-_u39-pad3_ d_nor +* u40 net-_u34-pad3_ net-_u34-pad3_ net-_u40-pad3_ d_nor +* u46 net-_u39-pad3_ net-_u40-pad3_ net-_u46-pad3_ d_nor +* u3 net-_u2-pad10_ net-_u12-pad1_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u4 net-_u2-pad11_ net-_u4-pad2_ d_inverter +* u6 net-_u2-pad12_ net-_u13-pad1_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u7 net-_u2-pad13_ net-_u14-pad1_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u8 net-_u2-pad14_ net-_u15-pad1_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u9 net-_u2-pad15_ net-_u16-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u2 net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u10-pad1_ adc_bridge_8 +* u11 net-_u1-pad9_ net-_u11-pad2_ adc_bridge_1 +* u54 net-_u52-pad1_ net-_u10-pad2_ net-_u52-pad2_ d_nand +* u52 net-_u52-pad1_ net-_u52-pad2_ net-_u47-pad3_ net-_u45-pad3_ net-_u46-pad3_ net-_u1-pad14_ net-_u1-pad13_ net-_u1-pad8_ net-_u1-pad7_ net-_u1-pad6_ dac_bridge_5 +* u51 net-_u50-pad3_ net-_u50-pad3_ net-_u51-pad3_ d_nand +a1 [net-_u11-pad2_ net-_u2-pad9_ ] net-_u23-pad3_ u23 +a2 [net-_u2-pad10_ net-_u2-pad11_ ] net-_u24-pad3_ u24 +a3 [net-_u2-pad12_ net-_u2-pad13_ ] net-_u25-pad3_ u25 +a4 [net-_u2-pad14_ net-_u2-pad15_ ] net-_u26-pad3_ u26 +a5 [net-_u23-pad3_ net-_u23-pad3_ ] net-_u29-pad3_ u29 +a6 [net-_u24-pad3_ net-_u24-pad3_ ] net-_u30-pad3_ u30 +a7 [net-_u25-pad3_ net-_u25-pad3_ ] net-_u31-pad3_ u31 +a8 [net-_u26-pad3_ net-_u26-pad3_ ] net-_u32-pad3_ u32 +a9 [net-_u29-pad3_ net-_u30-pad3_ ] net-_u41-pad3_ u41 +a10 [net-_u31-pad3_ net-_u32-pad3_ ] net-_u42-pad3_ u42 +a11 [net-_u41-pad3_ net-_u41-pad3_ ] net-_u48-pad3_ u48 +a12 [net-_u42-pad3_ net-_u42-pad3_ ] net-_u49-pad3_ u49 +a13 [net-_u48-pad3_ net-_u49-pad3_ ] net-_u50-pad3_ u50 +a14 [net-_u51-pad3_ net-_u10-pad2_ ] net-_u52-pad1_ u53 +a15 net-_u2-pad9_ net-_u5-pad2_ u5 +a16 [net-_u16-pad1_ net-_u10-pad2_ ] net-_u16-pad3_ u16 +a17 [net-_u35-pad1_ net-_u35-pad2_ ] net-_u35-pad3_ u35 +a18 [net-_u36-pad1_ net-_u16-pad3_ ] net-_u36-pad3_ u36 +a19 [net-_u35-pad3_ net-_u35-pad3_ ] net-_u43-pad3_ u43 +a20 [net-_u36-pad3_ net-_u36-pad3_ ] net-_u44-pad3_ u44 +a21 [net-_u43-pad3_ net-_u44-pad3_ ] net-_u47-pad3_ u47 +a22 [net-_u15-pad1_ net-_u10-pad2_ ] net-_u17-pad3_ u17 +a23 [net-_u16-pad1_ net-_u10-pad2_ ] net-_u18-pad3_ u18 +a24 [net-_u27-pad1_ net-_u27-pad2_ ] net-_u27-pad3_ u27 +a25 [net-_u17-pad3_ net-_u18-pad3_ ] net-_u28-pad3_ u28 +a26 [net-_u27-pad3_ net-_u27-pad3_ ] net-_u37-pad3_ u37 +a27 [net-_u28-pad3_ net-_u28-pad3_ ] net-_u38-pad3_ u38 +a28 [net-_u37-pad3_ net-_u38-pad3_ ] net-_u45-pad3_ u45 +a29 [net-_u13-pad1_ net-_u10-pad2_ ] net-_u19-pad3_ u19 +a30 [net-_u14-pad1_ net-_u10-pad2_ ] net-_u20-pad3_ u20 +a31 [net-_u15-pad1_ net-_u10-pad2_ ] net-_u21-pad3_ u21 +a32 [net-_u16-pad1_ net-_u10-pad2_ ] net-_u22-pad3_ u22 +a33 [net-_u19-pad3_ net-_u20-pad3_ ] net-_u33-pad3_ u33 +a34 [net-_u21-pad3_ net-_u22-pad3_ ] net-_u34-pad3_ u34 +a35 [net-_u33-pad3_ net-_u33-pad3_ ] net-_u39-pad3_ u39 +a36 [net-_u34-pad3_ net-_u34-pad3_ ] net-_u40-pad3_ u40 +a37 [net-_u39-pad3_ net-_u40-pad3_ ] net-_u46-pad3_ u46 +a38 net-_u2-pad10_ net-_u12-pad1_ u3 +a39 net-_u12-pad1_ net-_u12-pad2_ u12 +a40 net-_u2-pad11_ net-_u4-pad2_ u4 +a41 net-_u2-pad12_ net-_u13-pad1_ u6 +a42 net-_u13-pad1_ net-_u13-pad2_ u13 +a43 net-_u2-pad13_ net-_u14-pad1_ u7 +a44 net-_u14-pad1_ net-_u14-pad2_ u14 +a45 net-_u2-pad14_ net-_u15-pad1_ u8 +a46 net-_u15-pad1_ net-_u15-pad2_ u15 +a47 net-_u2-pad15_ net-_u16-pad1_ u9 +a48 net-_u10-pad1_ net-_u10-pad2_ u10 +a49 [net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ] [net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u10-pad1_ ] u2 +a50 [net-_u1-pad9_ ] [net-_u11-pad2_ ] u11 +a51 [net-_u52-pad1_ net-_u10-pad2_ ] net-_u52-pad2_ u54 +a52 [net-_u52-pad1_ net-_u52-pad2_ net-_u47-pad3_ net-_u45-pad3_ net-_u46-pad3_ ] [net-_u1-pad14_ net-_u1-pad13_ net-_u1-pad8_ net-_u1-pad7_ net-_u1-pad6_ ] u52 +a53 [net-_u50-pad3_ net-_u50-pad3_ ] net-_u51-pad3_ u51 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u25 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u26 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u29 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u30 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u31 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u32 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u41 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u42 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u48 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u49 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u50 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u53 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u35 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u36 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u43 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u44 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u47 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u27 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u28 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u38 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u45 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u33 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u34 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u39 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u40 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u46 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u11 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u54 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_5, NgSpice Name: dac_bridge +.model u52 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u51 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN74LS148_IC
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC_Previous_Values.xml new file mode 100644 index 00000000..6d21696c --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u23 name="type">d_nand<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u23><u24 name="type">d_nand<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u24><u25 name="type">d_nand<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u25><u26 name="type">d_nand<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u26><u29 name="type">d_nand<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u29><u30 name="type">d_nand<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u30><u31 name="type">d_nand<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u31><u32 name="type">d_nand<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u32><u41 name="type">d_nand<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u41><u42 name="type">d_nand<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u42><u48 name="type">d_nand<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u48><u49 name="type">d_nand<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u49><u50 name="type">d_nand<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u50><u53 name="type">d_nand<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u53><u5 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u5><u16 name="type">d_and<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u16><u35 name="type">d_nor<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u35><u36 name="type">d_nor<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u36><u43 name="type">d_nor<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u43><u44 name="type">d_nor<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u44><u47 name="type">d_nor<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u47><u17 name="type">d_and<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u17><u18 name="type">d_and<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u18><u27 name="type">d_nor<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u27><u28 name="type">d_nor<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u28><u37 name="type">d_nor<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u37><u38 name="type">d_nor<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u38><u45 name="type">d_nor<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u45><u19 name="type">d_and<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u19><u20 name="type">d_and<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_and<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Fall Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u21><u22 name="type">d_and<field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Fall Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /></u22><u33 name="type">d_nor<field97 name="Enter Rise Delay (default=1.0e-9)" /><field98 name="Enter Fall Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /></u33><u34 name="type">d_nor<field100 name="Enter Rise Delay (default=1.0e-9)" /><field101 name="Enter Fall Delay (default=1.0e-9)" /><field102 name="Enter Input Load (default=1.0e-12)" /></u34><u39 name="type">d_nor<field103 name="Enter Rise Delay (default=1.0e-9)" /><field104 name="Enter Fall Delay (default=1.0e-9)" /><field105 name="Enter Input Load (default=1.0e-12)" /></u39><u40 name="type">d_nor<field106 name="Enter Rise Delay (default=1.0e-9)" /><field107 name="Enter Fall Delay (default=1.0e-9)" /><field108 name="Enter Input Load (default=1.0e-12)" /></u40><u46 name="type">d_nor<field109 name="Enter Rise Delay (default=1.0e-9)" /><field110 name="Enter Fall Delay (default=1.0e-9)" /><field111 name="Enter Input Load (default=1.0e-12)" /></u46><u3 name="type">d_inverter<field112 name="Enter Rise Delay (default=1.0e-9)" /><field113 name="Enter Fall Delay (default=1.0e-9)" /><field114 name="Enter Input Load (default=1.0e-12)" /></u3><u12 name="type">d_inverter<field115 name="Enter Rise Delay (default=1.0e-9)" /><field116 name="Enter Fall Delay (default=1.0e-9)" /><field117 name="Enter Input Load (default=1.0e-12)" /></u12><u4 name="type">d_inverter<field118 name="Enter Rise Delay (default=1.0e-9)" /><field119 name="Enter Fall Delay (default=1.0e-9)" /><field120 name="Enter Input Load (default=1.0e-12)" /></u4><u6 name="type">d_inverter<field121 name="Enter Rise Delay (default=1.0e-9)" /><field122 name="Enter Fall Delay (default=1.0e-9)" /><field123 name="Enter Input Load (default=1.0e-12)" /></u6><u13 name="type">d_inverter<field124 name="Enter Rise Delay (default=1.0e-9)" /><field125 name="Enter Fall Delay (default=1.0e-9)" /><field126 name="Enter Input Load (default=1.0e-12)" /></u13><u7 name="type">d_inverter<field127 name="Enter Rise Delay (default=1.0e-9)" /><field128 name="Enter Fall Delay (default=1.0e-9)" /><field129 name="Enter Input Load (default=1.0e-12)" /></u7><u14 name="type">d_inverter<field130 name="Enter Rise Delay (default=1.0e-9)" /><field131 name="Enter Fall Delay (default=1.0e-9)" /><field132 name="Enter Input Load (default=1.0e-12)" /></u14><u8 name="type">d_inverter<field133 name="Enter Rise Delay (default=1.0e-9)" /><field134 name="Enter Fall Delay (default=1.0e-9)" /><field135 name="Enter Input Load (default=1.0e-12)" /></u8><u15 name="type">d_inverter<field136 name="Enter Rise Delay (default=1.0e-9)" /><field137 name="Enter Fall Delay (default=1.0e-9)" /><field138 name="Enter Input Load (default=1.0e-12)" /></u15><u9 name="type">d_inverter<field139 name="Enter Rise Delay (default=1.0e-9)" /><field140 name="Enter Fall Delay (default=1.0e-9)" /><field141 name="Enter Input Load (default=1.0e-12)" /></u9><u10 name="type">d_inverter<field142 name="Enter Rise Delay (default=1.0e-9)" /><field143 name="Enter Fall Delay (default=1.0e-9)" /><field144 name="Enter Input Load (default=1.0e-12)" /></u10><u2 name="type">adc_bridge<field145 name="Enter value for in_low (default=1.0)" /><field146 name="Enter value for in_high (default=2.0)" /><field147 name="Enter Rise Delay (default=1.0e-9)" /><field148 name="Enter Fall Delay (default=1.0e-9)" /></u2><u11 name="type">adc_bridge<field149 name="Enter value for in_low (default=1.0)" /><field150 name="Enter value for in_high (default=2.0)" /><field151 name="Enter Rise Delay (default=1.0e-9)" /><field152 name="Enter Fall Delay (default=1.0e-9)" /></u11><u54 name="type">d_nand<field153 name="Enter Rise Delay (default=1.0e-9)" /><field154 name="Enter Fall Delay (default=1.0e-9)" /><field155 name="Enter Input Load (default=1.0e-12)" /></u54><u52 name="type">dac_bridge<field156 name="Enter value for out_low (default=0.0)" /><field157 name="Enter value for out_high (default=5.0)" /><field158 name="Enter value for out_undef (default=0.5)" /><field159 name="Enter value for input load (default=1.0e-12)" /><field160 name="Enter the Rise Time (default=1.0e-9)" /><field161 name="Enter the Fall Time (default=1.0e-9)" /></u52><u51 name="type">d_nand<field162 name="Enter Rise Delay (default=1.0e-9)" /><field163 name="Enter Fall Delay (default=1.0e-9)" /><field164 name="Enter Input Load (default=1.0e-12)" /></u51></model><devicemodel /><subcircuit><x5><field>D:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x5><x2><field>D:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x2><x1><field>D:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x1><x3><field>D:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x3><x4><field>D:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x4></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS148_sub/analysis b/library/SubcircuitLibrary/SN74LS148_sub/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file |