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author | AnkushECE | 2022-08-24 22:55:29 +0530 |
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committer | AnkushECE | 2022-08-24 22:55:29 +0530 |
commit | 6996111988e740ae0283746398cacce78d4be6e7 (patch) | |
tree | 6616ad7d0e573aa4a233eb3097069a10d98d5e80 /library | |
parent | e3d6e33a22a75efba2edbce316324836015190e7 (diff) | |
download | eSim-6996111988e740ae0283746398cacce78d4be6e7.tar.gz eSim-6996111988e740ae0283746398cacce78d4be6e7.tar.bz2 eSim-6996111988e740ae0283746398cacce78d4be6e7.zip |
CD4071 is OR gate IC.
Diffstat (limited to 'library')
-rw-r--r-- | library/SubcircuitLibrary/CD_4071/CD_4071-cache.lib | 100 | ||||
-rw-r--r-- | library/SubcircuitLibrary/CD_4071/CD_4071.cir | 35 | ||||
-rw-r--r-- | library/SubcircuitLibrary/CD_4071/CD_4071.cir.out | 38 | ||||
-rw-r--r-- | library/SubcircuitLibrary/CD_4071/CD_4071.pro | 71 | ||||
-rw-r--r-- | library/SubcircuitLibrary/CD_4071/CD_4071.sch | 845 | ||||
-rw-r--r-- | library/SubcircuitLibrary/CD_4071/CD_4071.sub | 32 | ||||
-rw-r--r-- | library/SubcircuitLibrary/CD_4071/CD_4071_Previous_Values.xml | 1 | ||||
-rw-r--r-- | library/SubcircuitLibrary/CD_4071/NMOS-180nm.lib | 13 | ||||
-rw-r--r-- | library/SubcircuitLibrary/CD_4071/PMOS-180nm.lib | 11 | ||||
-rw-r--r-- | library/SubcircuitLibrary/CD_4071/README.md | 30 | ||||
-rw-r--r-- | library/SubcircuitLibrary/CD_4071/analysis | 1 |
11 files changed, 1177 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/CD_4071/CD_4071-cache.lib b/library/SubcircuitLibrary/CD_4071/CD_4071-cache.lib new file mode 100644 index 00000000..6c512720 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4071/CD_4071-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD_4071/CD_4071.cir b/library/SubcircuitLibrary/CD_4071/CD_4071.cir new file mode 100644 index 00000000..03d0d508 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4071/CD_4071.cir @@ -0,0 +1,35 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD_4071\CD_4071.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/20/22 11:07:38 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M3 Net-_M3-Pad1_ Net-_M1-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M4 Net-_M1-Pad1_ Net-_M4-Pad2_ Net-_M3-Pad1_ Net-_M3-Pad1_ eSim_MOS_P +M7 Net-_M1-Pad1_ Net-_M4-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M11 Net-_M11-Pad1_ Net-_M1-Pad1_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M9 Net-_M11-Pad1_ Net-_M1-Pad1_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M15 Net-_M15-Pad1_ Net-_M13-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M13 Net-_M13-Pad1_ Net-_M13-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M16 Net-_M13-Pad1_ Net-_M16-Pad2_ Net-_M15-Pad1_ Net-_M15-Pad1_ eSim_MOS_P +M19 Net-_M13-Pad1_ Net-_M16-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M23 Net-_M21-Pad1_ Net-_M13-Pad1_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M21 Net-_M21-Pad1_ Net-_M13-Pad1_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M5 Net-_M5-Pad1_ Net-_M2-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M2 Net-_M10-Pad2_ Net-_M2-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M6 Net-_M10-Pad2_ Net-_M6-Pad2_ Net-_M5-Pad1_ Net-_M5-Pad1_ eSim_MOS_P +M8 Net-_M10-Pad2_ Net-_M6-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M12 Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M10 Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M17 Net-_M17-Pad1_ Net-_M14-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M14 Net-_M14-Pad1_ Net-_M14-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M18 Net-_M14-Pad1_ Net-_M18-Pad2_ Net-_M17-Pad1_ Net-_M17-Pad1_ eSim_MOS_P +M20 Net-_M14-Pad1_ Net-_M18-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M24 Net-_M22-Pad1_ Net-_M14-Pad1_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M22 Net-_M22-Pad1_ Net-_M14-Pad1_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +U1 Net-_M2-Pad2_ Net-_M6-Pad2_ Net-_M10-Pad1_ Net-_M22-Pad1_ Net-_M14-Pad2_ Net-_M18-Pad2_ Net-_M1-Pad3_ Net-_M13-Pad2_ Net-_M16-Pad2_ Net-_M21-Pad1_ Net-_M11-Pad1_ Net-_M1-Pad2_ Net-_M4-Pad2_ Net-_M11-Pad3_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD_4071/CD_4071.cir.out b/library/SubcircuitLibrary/CD_4071/CD_4071.cir.out new file mode 100644 index 00000000..27410a17 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4071/CD_4071.cir.out @@ -0,0 +1,38 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd_4071\cd_4071.cir + +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m3 net-_m3-pad1_ net-_m1-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m4 net-_m1-pad1_ net-_m4-pad2_ net-_m3-pad1_ net-_m3-pad1_ CMOSP W=100u L=100u M=1 +m7 net-_m1-pad1_ net-_m4-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m11 net-_m11-pad1_ net-_m1-pad1_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m9 net-_m11-pad1_ net-_m1-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m15 net-_m15-pad1_ net-_m13-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m13 net-_m13-pad1_ net-_m13-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m16 net-_m13-pad1_ net-_m16-pad2_ net-_m15-pad1_ net-_m15-pad1_ CMOSP W=100u L=100u M=1 +m19 net-_m13-pad1_ net-_m16-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m23 net-_m21-pad1_ net-_m13-pad1_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m21 net-_m21-pad1_ net-_m13-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m5 net-_m5-pad1_ net-_m2-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m2 net-_m10-pad2_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m10-pad2_ net-_m6-pad2_ net-_m5-pad1_ net-_m5-pad1_ CMOSP W=100u L=100u M=1 +m8 net-_m10-pad2_ net-_m6-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m12 net-_m10-pad1_ net-_m10-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m17 net-_m17-pad1_ net-_m14-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m14 net-_m14-pad1_ net-_m14-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m18 net-_m14-pad1_ net-_m18-pad2_ net-_m17-pad1_ net-_m17-pad1_ CMOSP W=100u L=100u M=1 +m20 net-_m14-pad1_ net-_m18-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m24 net-_m22-pad1_ net-_m14-pad1_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m22 net-_m22-pad1_ net-_m14-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +* u1 net-_m2-pad2_ net-_m6-pad2_ net-_m10-pad1_ net-_m22-pad1_ net-_m14-pad2_ net-_m18-pad2_ net-_m1-pad3_ net-_m13-pad2_ net-_m16-pad2_ net-_m21-pad1_ net-_m11-pad1_ net-_m1-pad2_ net-_m4-pad2_ net-_m11-pad3_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD_4071/CD_4071.pro b/library/SubcircuitLibrary/CD_4071/CD_4071.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/CD_4071/CD_4071.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/CD_4071/CD_4071.sch b/library/SubcircuitLibrary/CD_4071/CD_4071.sch new file mode 100644 index 00000000..1aca01d6 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4071/CD_4071.sch @@ -0,0 +1,845 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:CD_4071-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_MOS_P M3 +U 1 1 628727AE +P 3100 1750 +F 0 "M3" H 3050 1800 50 0000 R CNN +F 1 "eSim_MOS_P" H 3150 1900 50 0000 R CNN +F 2 "" H 3350 1850 29 0000 C CNN +F 3 "" H 3150 1750 60 0000 C CNN + 1 3100 1750 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M1 +U 1 1 628727AF +P 2700 2800 +F 0 "M1" H 2700 2650 50 0000 R CNN +F 1 "eSim_MOS_N" H 2800 2750 50 0000 R CNN +F 2 "" H 3000 2500 29 0000 C CNN +F 3 "" H 2800 2600 60 0000 C CNN + 1 2700 2800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M4 +U 1 1 628727B0 +P 3100 2300 +F 0 "M4" H 3050 2350 50 0000 R CNN +F 1 "eSim_MOS_P" H 3150 2450 50 0000 R CNN +F 2 "" H 3350 2400 29 0000 C CNN +F 3 "" H 3150 2300 60 0000 C CNN + 1 3100 2300 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M7 +U 1 1 628727B1 +P 3850 2800 +F 0 "M7" H 3850 2650 50 0000 R CNN +F 1 "eSim_MOS_N" H 3950 2750 50 0000 R CNN +F 2 "" H 4150 2500 29 0000 C CNN +F 3 "" H 3950 2600 60 0000 C CNN + 1 3850 2800 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M11 +U 1 1 628727B2 +P 4800 2350 +F 0 "M11" H 4750 2400 50 0000 R CNN +F 1 "eSim_MOS_P" H 4850 2500 50 0000 R CNN +F 2 "" H 5050 2450 29 0000 C CNN +F 3 "" H 4850 2350 60 0000 C CNN + 1 4800 2350 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M9 +U 1 1 628727B3 +P 4750 2800 +F 0 "M9" H 4750 2650 50 0000 R CNN +F 1 "eSim_MOS_N" H 4850 2750 50 0000 R CNN +F 2 "" H 5050 2500 29 0000 C CNN +F 3 "" H 4850 2600 60 0000 C CNN + 1 4750 2800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3250 1950 3250 2100 +Wire Wire Line + 2900 3200 2900 3300 +Wire Wire Line + 2900 3300 3650 3300 +Wire Wire Line + 3650 3300 3650 3200 +Wire Wire Line + 2900 2800 2900 2750 +Wire Wire Line + 2900 2750 3650 2750 +Wire Wire Line + 3650 2750 3650 2800 +Wire Wire Line + 3250 2500 3250 2750 +Connection ~ 3250 2750 +Wire Wire Line + 3000 3150 3000 3300 +Connection ~ 3000 3300 +Wire Wire Line + 3550 3150 3550 3300 +Connection ~ 3550 3300 +Wire Wire Line + 4950 2550 4950 2800 +Wire Wire Line + 4650 2350 4600 2350 +Wire Wire Line + 4600 2350 4600 3000 +Wire Wire Line + 4600 3000 4650 3000 +Wire Wire Line + 4950 2150 5050 2150 +Wire Wire Line + 5050 2150 5050 2200 +Wire Wire Line + 4950 3200 5050 3200 +Wire Wire Line + 5050 3200 5050 3150 +Wire Wire Line + 3250 1550 3350 1550 +Wire Wire Line + 3350 1550 3350 1600 +Wire Wire Line + 3350 2150 3350 2050 +Wire Wire Line + 3350 2050 3250 2050 +Connection ~ 3250 2050 +Wire Wire Line + 3250 2600 4600 2600 +Connection ~ 4600 2600 +Connection ~ 3250 2600 +Wire Wire Line + 2950 1750 2500 1750 +Wire Wire Line + 2500 1750 2500 3000 +Wire Wire Line + 2500 3000 2600 3000 +Wire Wire Line + 2950 2300 2950 2500 +Wire Wire Line + 2200 2500 3950 2500 +Wire Wire Line + 3950 2500 3950 3000 +Wire Wire Line + 2500 2350 2200 2350 +Connection ~ 2500 2350 +Connection ~ 2950 2500 +Wire Wire Line + 3300 1550 3300 1500 +Wire Wire Line + 3300 1500 5000 1500 +Wire Wire Line + 5000 1500 5000 2150 +Connection ~ 5000 2150 +Connection ~ 3300 1550 +Wire Wire Line + 3250 3300 3250 3350 +Wire Wire Line + 3250 3350 8450 3350 +Wire Wire Line + 5000 3350 5000 3200 +Connection ~ 5000 3200 +Connection ~ 3250 3300 +Wire Wire Line + 4950 2650 5250 2650 +Connection ~ 4950 2650 +$Comp +L eSim_MOS_P M15 +U 1 1 628727B4 +P 6550 1750 +F 0 "M15" H 6500 1800 50 0000 R CNN +F 1 "eSim_MOS_P" H 6600 1900 50 0000 R CNN +F 2 "" H 6800 1850 29 0000 C CNN +F 3 "" H 6600 1750 60 0000 C CNN + 1 6550 1750 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M13 +U 1 1 628727B5 +P 6150 2800 +F 0 "M13" H 6150 2650 50 0000 R CNN +F 1 "eSim_MOS_N" H 6250 2750 50 0000 R CNN +F 2 "" H 6450 2500 29 0000 C CNN +F 3 "" H 6250 2600 60 0000 C CNN + 1 6150 2800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M16 +U 1 1 628727B6 +P 6550 2300 +F 0 "M16" H 6500 2350 50 0000 R CNN +F 1 "eSim_MOS_P" H 6600 2450 50 0000 R CNN +F 2 "" H 6800 2400 29 0000 C CNN +F 3 "" H 6600 2300 60 0000 C CNN + 1 6550 2300 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M19 +U 1 1 628727B7 +P 7300 2800 +F 0 "M19" H 7300 2650 50 0000 R CNN +F 1 "eSim_MOS_N" H 7400 2750 50 0000 R CNN +F 2 "" H 7600 2500 29 0000 C CNN +F 3 "" H 7400 2600 60 0000 C CNN + 1 7300 2800 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M23 +U 1 1 628727B8 +P 8250 2350 +F 0 "M23" H 8200 2400 50 0000 R CNN +F 1 "eSim_MOS_P" H 8300 2500 50 0000 R CNN +F 2 "" H 8500 2450 29 0000 C CNN +F 3 "" H 8300 2350 60 0000 C CNN + 1 8250 2350 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M21 +U 1 1 628727B9 +P 8200 2800 +F 0 "M21" H 8200 2650 50 0000 R CNN +F 1 "eSim_MOS_N" H 8300 2750 50 0000 R CNN +F 2 "" H 8500 2500 29 0000 C CNN +F 3 "" H 8300 2600 60 0000 C CNN + 1 8200 2800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6700 1950 6700 2100 +Wire Wire Line + 6350 3200 6350 3300 +Wire Wire Line + 6350 3300 7100 3300 +Wire Wire Line + 7100 3300 7100 3200 +Wire Wire Line + 6350 2800 6350 2750 +Wire Wire Line + 6350 2750 7100 2750 +Wire Wire Line + 7100 2750 7100 2800 +Wire Wire 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+Connection ~ 5000 3350 +Connection ~ 6700 5550 +Connection ~ 5000 5550 +Wire Wire Line + 5450 1400 5450 3650 +Connection ~ 5450 3650 +Connection ~ 5450 1400 +Wire Wire Line + 5550 3350 5550 5750 +Connection ~ 5550 5550 +Connection ~ 5550 3350 +$Comp +L PORT U1 +U 1 1 6287296A +P 1950 4550 +F 0 "U1" H 2000 4650 30 0000 C CNN +F 1 "PORT" H 1950 4550 30 0000 C CNN +F 2 "" H 1950 4550 60 0000 C CNN +F 3 "" H 1950 4550 60 0000 C CNN + 1 1950 4550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 62872A2C +P 1950 4700 +F 0 "U1" H 2000 4800 30 0000 C CNN +F 1 "PORT" H 1950 4700 30 0000 C CNN +F 2 "" H 1950 4700 60 0000 C CNN +F 3 "" H 1950 4700 60 0000 C CNN + 2 1950 4700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 62872A8F +P 5500 4850 +F 0 "U1" H 5550 4950 30 0000 C CNN +F 1 "PORT" H 5500 4850 30 0000 C CNN +F 2 "" H 5500 4850 60 0000 C CNN +F 3 "" H 5500 4850 60 0000 C CNN + 3 5500 4850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 62872B0A +P 8950 4850 +F 0 "U1" H 9000 4950 30 0000 C CNN +F 1 "PORT" H 8950 4850 30 0000 C CNN +F 2 "" H 8950 4850 60 0000 C CNN +F 3 "" H 8950 4850 60 0000 C CNN + 4 8950 4850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 62872C19 +P 5400 4550 +F 0 "U1" H 5450 4650 30 0000 C CNN +F 1 "PORT" H 5400 4550 30 0000 C CNN +F 2 "" H 5400 4550 60 0000 C CNN +F 3 "" H 5400 4550 60 0000 C CNN + 5 5400 4550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 62872CBA +P 5400 4700 +F 0 "U1" H 5450 4800 30 0000 C CNN +F 1 "PORT" H 5400 4700 30 0000 C CNN +F 2 "" H 5400 4700 60 0000 C CNN +F 3 "" H 5400 4700 60 0000 C CNN + 6 5400 4700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 62872D4F +P 5300 5750 +F 0 "U1" H 5350 5850 30 0000 C CNN +F 1 "PORT" H 5300 5750 30 0000 C CNN +F 2 "" H 5300 5750 60 0000 C CNN +F 3 "" H 5300 5750 60 0000 C CNN + 7 5300 5750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 62872F3E +P 5400 2350 +F 0 "U1" H 5450 2450 30 0000 C CNN +F 1 "PORT" H 5400 2350 30 0000 C CNN +F 2 "" H 5400 2350 60 0000 C CNN +F 3 "" H 5400 2350 60 0000 C CNN + 8 5400 2350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 62872FF3 +P 5400 2500 +F 0 "U1" H 5450 2600 30 0000 C CNN +F 1 "PORT" H 5400 2500 30 0000 C CNN +F 2 "" H 5400 2500 60 0000 C CNN +F 3 "" H 5400 2500 60 0000 C CNN + 9 5400 2500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 628730B4 +P 8950 2650 +F 0 "U1" H 9000 2750 30 0000 C CNN +F 1 "PORT" H 8950 2650 30 0000 C CNN +F 2 "" H 8950 2650 60 0000 C CNN +F 3 "" H 8950 2650 60 0000 C CNN + 10 8950 2650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 6287314B +P 5500 2650 +F 0 "U1" H 5550 2750 30 0000 C CNN +F 1 "PORT" H 5500 2650 30 0000 C CNN +F 2 "" H 5500 2650 60 0000 C CNN +F 3 "" H 5500 2650 60 0000 C CNN + 11 5500 2650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 6287321E +P 1950 2350 +F 0 "U1" H 2000 2450 30 0000 C CNN +F 1 "PORT" H 1950 2350 30 0000 C CNN +F 2 "" H 1950 2350 60 0000 C CNN +F 3 "" H 1950 2350 60 0000 C CNN + 12 1950 2350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 628732C3 +P 1950 2500 +F 0 "U1" H 2000 2600 30 0000 C CNN +F 1 "PORT" H 1950 2500 30 0000 C CNN +F 2 "" H 1950 2500 60 0000 C CNN +F 3 "" H 1950 2500 60 0000 C CNN + 13 1950 2500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 628739BA +P 3900 1400 +F 0 "U1" H 3950 1500 30 0000 C CNN +F 1 "PORT" H 3900 1400 30 0000 C CNN +F 2 "" H 3900 1400 60 0000 C CNN +F 3 "" H 3900 1400 60 0000 C CNN + 14 3900 1400 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD_4071/CD_4071.sub b/library/SubcircuitLibrary/CD_4071/CD_4071.sub new file mode 100644 index 00000000..973024dd --- /dev/null +++ b/library/SubcircuitLibrary/CD_4071/CD_4071.sub @@ -0,0 +1,32 @@ +* Subcircuit CD_4071 +.subckt CD_4071 net-_m2-pad2_ net-_m6-pad2_ net-_m10-pad1_ net-_m22-pad1_ net-_m14-pad2_ net-_m18-pad2_ net-_m1-pad3_ net-_m13-pad2_ net-_m16-pad2_ net-_m21-pad1_ net-_m11-pad1_ net-_m1-pad2_ net-_m4-pad2_ net-_m11-pad3_ +* c:\fossee\esim\library\subcircuitlibrary\cd_4071\cd_4071.cir +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m3 net-_m3-pad1_ net-_m1-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m4 net-_m1-pad1_ net-_m4-pad2_ net-_m3-pad1_ net-_m3-pad1_ CMOSP W=100u L=100u M=1 +m7 net-_m1-pad1_ net-_m4-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m11 net-_m11-pad1_ net-_m1-pad1_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m9 net-_m11-pad1_ net-_m1-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m15 net-_m15-pad1_ net-_m13-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m13 net-_m13-pad1_ net-_m13-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m16 net-_m13-pad1_ net-_m16-pad2_ net-_m15-pad1_ net-_m15-pad1_ CMOSP W=100u L=100u M=1 +m19 net-_m13-pad1_ net-_m16-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m23 net-_m21-pad1_ net-_m13-pad1_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m21 net-_m21-pad1_ net-_m13-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m5 net-_m5-pad1_ net-_m2-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m2 net-_m10-pad2_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m10-pad2_ net-_m6-pad2_ net-_m5-pad1_ net-_m5-pad1_ CMOSP W=100u L=100u M=1 +m8 net-_m10-pad2_ net-_m6-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m12 net-_m10-pad1_ net-_m10-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m17 net-_m17-pad1_ net-_m14-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m14 net-_m14-pad1_ net-_m14-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m18 net-_m14-pad1_ net-_m18-pad2_ net-_m17-pad1_ net-_m17-pad1_ CMOSP W=100u L=100u M=1 +m20 net-_m14-pad1_ net-_m18-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m24 net-_m22-pad1_ net-_m14-pad1_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m22 net-_m22-pad1_ net-_m14-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +* Control Statements + +.ends CD_4071
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD_4071/CD_4071_Previous_Values.xml b/library/SubcircuitLibrary/CD_4071/CD_4071_Previous_Values.xml new file mode 100644 index 00000000..942286c7 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4071/CD_4071_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model /><devicemodel><m3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m3><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m1><m4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m4><m7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m7><m11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m11><m9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m9><m15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m15><m13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m13><m16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m16><m19><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m19><m23><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m23><m21><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m21><m5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m5><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m2><m6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m6><m8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m8><m12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m12><m10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m10><m17><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m17><m14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m14><m18><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m18><m20><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m20><m24><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m24><m22><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m22></devicemodel><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD_4071/NMOS-180nm.lib b/library/SubcircuitLibrary/CD_4071/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4071/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/CD_4071/PMOS-180nm.lib b/library/SubcircuitLibrary/CD_4071/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4071/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/CD_4071/README.md b/library/SubcircuitLibrary/CD_4071/README.md new file mode 100644 index 00000000..9f99fe20 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4071/README.md @@ -0,0 +1,30 @@ + +# CD4071 IC + +It is 2-input OR Gate IC. CD4071 IC is designed with 180nm CMOS technology in eSim consisting four OR Gates. When both the inputs are LOW then only output is LOW, otherwise HIGH. + + +## Usage/Examples + +In designing basic logic circuits or Alarm circuits for example alarm for a car door system can be designed using this IC. + +Encoders + +Decoders + +We can design Multiplexers of any size and also De-multiplexers. + +## Documentation + +To know the details of CD4071 IC please go through with the documentation : [CD4071_datasheet](https://www.ti.com/lit/gpn/cd4071b) + +## Comments/Notes + +Please note this is a complete digital IC. It works fine at the time of simulation. + +## Contributer + +Name: Ankush Mondal +Email: mondalankush369@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellow 2022
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD_4071/analysis b/library/SubcircuitLibrary/CD_4071/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4071/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file |