diff options
author | Sumanto Kar | 2025-02-23 17:37:05 +0530 |
---|---|---|
committer | GitHub | 2025-02-23 17:37:05 +0530 |
commit | 311d0244d6093ebdccee00d072016b7a7a1c9372 (patch) | |
tree | 02f10e99abea8736d02fc46a12895bcad2743cf6 /library/SubcircuitLibrary/mc1489A_0 | |
parent | ae99d42b8d2ffeaf91f96d5ffbe5efe91214cf0c (diff) | |
parent | 053d7b4f66655f04b4965b26ffea0125cab1ccdd (diff) | |
download | eSim-master.tar.gz eSim-master.tar.bz2 eSim-master.zip |
Subcircuit files for different ICs
Diffstat (limited to 'library/SubcircuitLibrary/mc1489A_0')
-rw-r--r-- | library/SubcircuitLibrary/mc1489A_0/D.lib | 2 | ||||
-rw-r--r-- | library/SubcircuitLibrary/mc1489A_0/NPN.lib | 4 | ||||
-rw-r--r-- | library/SubcircuitLibrary/mc1489A_0/analysis | 1 | ||||
-rw-r--r-- | library/SubcircuitLibrary/mc1489A_0/mc1489A_0-cache.lib | 107 | ||||
-rw-r--r-- | library/SubcircuitLibrary/mc1489A_0/mc1489A_0.cir | 21 | ||||
-rw-r--r-- | library/SubcircuitLibrary/mc1489A_0/mc1489A_0.cir.out | 24 | ||||
-rw-r--r-- | library/SubcircuitLibrary/mc1489A_0/mc1489A_0.pro | 73 | ||||
-rw-r--r-- | library/SubcircuitLibrary/mc1489A_0/mc1489A_0.sch | 274 | ||||
-rw-r--r-- | library/SubcircuitLibrary/mc1489A_0/mc1489A_0.sub | 18 | ||||
-rw-r--r-- | library/SubcircuitLibrary/mc1489A_0/mc1489A_0_Previous_Values.xml | 1 |
10 files changed, 525 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/mc1489A_0/D.lib b/library/SubcircuitLibrary/mc1489A_0/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/mc1489A_0/NPN.lib b/library/SubcircuitLibrary/mc1489A_0/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/mc1489A_0/analysis b/library/SubcircuitLibrary/mc1489A_0/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/mc1489A_0/mc1489A_0-cache.lib b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0-cache.lib new file mode 100644 index 00000000..7e9c6731 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0-cache.lib @@ -0,0 +1,107 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.cir b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.cir new file mode 100644 index 00000000..7b3d76c7 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.cir @@ -0,0 +1,21 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\mc1489A_0\mc1489A_0.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/09/25 01:16:43 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_D1-Pad2_ Net-_D1-Pad1_ eSim_NPN +Q2 Net-_Q2-Pad1_ Net-_Q1-Pad1_ Net-_D1-Pad1_ eSim_NPN +Q3 Net-_Q3-Pad1_ Net-_Q2-Pad1_ Net-_D1-Pad1_ eSim_NPN +R2 Net-_D1-Pad2_ Net-_D1-Pad1_ 10K +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +R5 Net-_R4-Pad1_ Net-_Q2-Pad1_ 5K +R4 Net-_R4-Pad1_ Net-_Q1-Pad1_ 9K +R6 Net-_R4-Pad1_ Net-_Q3-Pad1_ 1.7K +R1 Net-_R1-Pad1_ Net-_D1-Pad2_ 3.8K +R3 Net-_D1-Pad2_ Net-_Q1-Pad1_ 1.6K +U1 Net-_R1-Pad1_ Net-_D1-Pad2_ Net-_R4-Pad1_ Net-_Q3-Pad1_ Net-_D1-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.cir.out b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.cir.out new file mode 100644 index 00000000..6fa09c26 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.cir.out @@ -0,0 +1,24 @@ +* c:\fossee\esim\library\subcircuitlibrary\mc1489a_0\mc1489a_0.cir + +.include NPN.lib +.include D.lib +q1 net-_q1-pad1_ net-_d1-pad2_ net-_d1-pad1_ Q2N2222 +q2 net-_q2-pad1_ net-_q1-pad1_ net-_d1-pad1_ Q2N2222 +q3 net-_q3-pad1_ net-_q2-pad1_ net-_d1-pad1_ Q2N2222 +r2 net-_d1-pad2_ net-_d1-pad1_ 10k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r5 net-_r4-pad1_ net-_q2-pad1_ 5k +r4 net-_r4-pad1_ net-_q1-pad1_ 9k +r6 net-_r4-pad1_ net-_q3-pad1_ 1.7k +r1 net-_r1-pad1_ net-_d1-pad2_ 3.8k +r3 net-_d1-pad2_ net-_q1-pad1_ 1.6k +* u1 net-_r1-pad1_ net-_d1-pad2_ net-_r4-pad1_ net-_q3-pad1_ net-_d1-pad1_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.pro b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.sch b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.sch new file mode 100644 index 00000000..d247d45d --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.sch @@ -0,0 +1,274 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 679A2F36 +P 5550 4050 +F 0 "Q1" H 5450 4100 50 0000 R CNN +F 1 "eSim_NPN" H 5500 4200 50 0000 R CNN +F 2 "" H 5750 4150 29 0000 C CNN +F 3 "" H 5550 4050 60 0000 C CNN + 1 5550 4050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 679A2F55 +P 6350 3850 +F 0 "Q2" H 6250 3900 50 0000 R CNN +F 1 "eSim_NPN" H 6300 4000 50 0000 R CNN +F 2 "" H 6550 3950 29 0000 C CNN +F 3 "" H 6350 3850 60 0000 C CNN + 1 6350 3850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 679A2F6E +P 7300 3650 +F 0 "Q3" H 7200 3700 50 0000 R CNN +F 1 "eSim_NPN" H 7250 3800 50 0000 R CNN +F 2 "" H 7500 3750 29 0000 C CNN +F 3 "" H 7300 3650 60 0000 C CNN + 1 7300 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5350 3850 6150 3850 +Wire Wire Line + 6450 3650 7100 3650 +$Comp +L resistor R2 +U 1 1 679A2F98 +P 4950 4300 +F 0 "R2" H 5000 4430 50 0000 C CNN +F 1 "10K" H 5000 4250 50 0000 C CNN +F 2 "" H 5000 4280 30 0000 C CNN +F 3 "" V 5000 4350 30 0000 C CNN + 1 4950 4300 + 0 1 1 0 +$EndComp +Wire Wire Line + 5000 3850 5000 4200 +Wire Wire Line + 3900 4050 5350 4050 +Wire Wire Line + 5000 4500 5000 4600 +Wire Wire Line + 4500 4600 8100 4600 +Wire Wire Line + 5650 4600 5650 4250 +Wire Wire Line + 6450 4600 6450 4050 +Connection ~ 5650 4600 +Wire Wire Line + 7400 4600 7400 3850 +Connection ~ 6450 4600 +$Comp +L eSim_Diode D1 +U 1 1 679A2FEE +P 4500 4350 +F 0 "D1" H 4500 4450 50 0000 C CNN +F 1 "eSim_Diode" H 4500 4250 50 0000 C CNN +F 2 "" H 4500 4350 60 0000 C CNN +F 3 "" H 4500 4350 60 0000 C CNN + 1 4500 4350 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 4500 4500 4500 4600 +Connection ~ 5000 4600 +Wire Wire Line + 4500 4200 4500 4050 +Connection ~ 5000 4050 +$Comp +L resistor R5 +U 1 1 679A303B +P 6400 3150 +F 0 "R5" H 6450 3280 50 0000 C CNN +F 1 "5K" H 6450 3100 50 0000 C CNN +F 2 "" H 6450 3130 30 0000 C CNN +F 3 "" V 6450 3200 30 0000 C CNN + 1 6400 3150 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 679A3060 +P 5600 3200 +F 0 "R4" H 5650 3330 50 0000 C CNN +F 1 "9K" H 5650 3150 50 0000 C CNN +F 2 "" H 5650 3180 30 0000 C CNN +F 3 "" V 5650 3250 30 0000 C CNN + 1 5600 3200 + 0 1 1 0 +$EndComp +$Comp +L resistor R6 +U 1 1 679A3095 +P 7350 3150 +F 0 "R6" H 7400 3280 50 0000 C CNN +F 1 "1.7K" H 7400 3100 50 0000 C CNN +F 2 "" H 7400 3130 30 0000 C CNN +F 3 "" V 7400 3200 30 0000 C CNN + 1 7350 3150 + 0 1 1 0 +$EndComp +Wire Wire Line + 5650 3400 5650 3850 +Wire Wire Line + 6450 3350 6450 3650 +Wire Wire Line + 7400 3350 7400 3450 +Wire Wire Line + 5650 3100 5650 2900 +Wire Wire Line + 5650 2900 7950 2900 +Wire Wire Line + 7400 2900 7400 3050 +Wire Wire Line + 6450 3050 6450 2900 +Connection ~ 6450 2900 +Connection ~ 7400 2900 +Wire Wire Line + 7400 3400 8000 3400 +Connection ~ 7400 3400 +Connection ~ 7400 4600 +Connection ~ 4500 4050 +$Comp +L resistor R1 +U 1 1 679A31DB +P 3700 4100 +F 0 "R1" H 3750 4230 50 0000 C CNN +F 1 "3.8K" H 3750 4050 50 0000 C CNN +F 2 "" H 3750 4080 30 0000 C CNN +F 3 "" V 3750 4150 30 0000 C CNN + 1 3700 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3600 4050 3400 4050 +Connection ~ 5650 3850 +$Comp +L resistor R3 +U 1 1 679A3264 +P 5150 3900 +F 0 "R3" H 5200 4030 50 0000 C CNN +F 1 "1.6K" H 5200 3850 50 0000 C CNN +F 2 "" H 5200 3880 30 0000 C CNN +F 3 "" V 5200 3950 30 0000 C CNN + 1 5150 3900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3400 3850 5050 3850 +Connection ~ 5000 3850 +$Comp +L PORT U1 +U 3 1 679A336F +P 8200 2900 +F 0 "U1" H 8250 3000 30 0000 C CNN +F 1 "PORT" H 8200 2900 30 0000 C CNN +F 2 "" H 8200 2900 60 0000 C CNN +F 3 "" H 8200 2900 60 0000 C CNN + 3 8200 2900 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 679A33BE +P 8250 3400 +F 0 "U1" H 8300 3500 30 0000 C CNN +F 1 "PORT" H 8250 3400 30 0000 C CNN +F 2 "" H 8250 3400 60 0000 C CNN +F 3 "" H 8250 3400 60 0000 C CNN + 4 8250 3400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 679A33F1 +P 8350 4600 +F 0 "U1" H 8400 4700 30 0000 C CNN +F 1 "PORT" H 8350 4600 30 0000 C CNN +F 2 "" H 8350 4600 60 0000 C CNN +F 3 "" H 8350 4600 60 0000 C CNN + 5 8350 4600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 679A3424 +P 3150 3850 +F 0 "U1" H 3200 3950 30 0000 C CNN +F 1 "PORT" H 3150 3850 30 0000 C CNN +F 2 "" H 3150 3850 60 0000 C CNN +F 3 "" H 3150 3850 60 0000 C CNN + 2 3150 3850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 679A3455 +P 3150 4050 +F 0 "U1" H 3200 4150 30 0000 C CNN +F 1 "PORT" H 3150 4050 30 0000 C CNN +F 2 "" H 3150 4050 60 0000 C CNN +F 3 "" H 3150 4050 60 0000 C CNN + 1 3150 4050 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.sub b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.sub new file mode 100644 index 00000000..e9ebfc80 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.sub @@ -0,0 +1,18 @@ +* Subcircuit mc1489A_0 +.subckt mc1489A_0 net-_r1-pad1_ net-_d1-pad2_ net-_r4-pad1_ net-_q3-pad1_ net-_d1-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\mc1489a_0\mc1489a_0.cir +.include NPN.lib +.include D.lib +q1 net-_q1-pad1_ net-_d1-pad2_ net-_d1-pad1_ Q2N2222 +q2 net-_q2-pad1_ net-_q1-pad1_ net-_d1-pad1_ Q2N2222 +q3 net-_q3-pad1_ net-_q2-pad1_ net-_d1-pad1_ Q2N2222 +r2 net-_d1-pad2_ net-_d1-pad1_ 10k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r5 net-_r4-pad1_ net-_q2-pad1_ 5k +r4 net-_r4-pad1_ net-_q1-pad1_ 9k +r6 net-_r4-pad1_ net-_q3-pad1_ 1.7k +r1 net-_r1-pad1_ net-_d1-pad2_ 3.8k +r3 net-_d1-pad2_ net-_q1-pad1_ 1.6k +* Control Statements + +.ends mc1489A_0
\ No newline at end of file diff --git a/library/SubcircuitLibrary/mc1489A_0/mc1489A_0_Previous_Values.xml b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0_Previous_Values.xml new file mode 100644 index 00000000..09ac9336 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file |