diff options
| author | Sumanto Kar | 2025-06-14 17:58:58 +0530 |
|---|---|---|
| committer | GitHub | 2025-06-14 17:58:58 +0530 |
| commit | eaf176100fc3c4eb20dab7f8293fa5d09f3409da (patch) | |
| tree | 19078474dd4fe389cb4a0496df56d2cf56fe2273 /library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.cir.out | |
| parent | 7975bc597123cab9d82f26262ea23f1e03282422 (diff) | |
| parent | fe3e9dcb6f62796ff392d7ec68febbd0a82e318b (diff) | |
| download | eSim-master.tar.gz eSim-master.tar.bz2 eSim-master.zip | |
Subcircuitfiles Files of ICs (Contributor : Shanthi priya)
Diffstat (limited to 'library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.cir.out')
| -rw-r--r-- | library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.cir.out | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.cir.out new file mode 100644 index 00000000..03c161c5 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.cir.out @@ -0,0 +1,36 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\jkff\jkff.cir + +* u2 net-_u1-pad5_ net-_u1-pad1_ net-_u2-pad3_ d_nand +* u4 net-_u2-pad3_ net-_u1-pad2_ net-_u4-pad3_ d_nand +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_nand +* u5 net-_u3-pad3_ net-_u1-pad2_ net-_u5-pad3_ d_nand +* u6 net-_u4-pad3_ net-_u1-pad5_ net-_u1-pad4_ d_nand +* u7 net-_u1-pad4_ net-_u5-pad3_ net-_u1-pad5_ d_nand +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad5_ net-_u1-pad1_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad2_ ] net-_u4-pad3_ u4 +a3 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a4 [net-_u3-pad3_ net-_u1-pad2_ ] net-_u5-pad3_ u5 +a5 [net-_u4-pad3_ net-_u1-pad5_ ] net-_u1-pad4_ u6 +a6 [net-_u1-pad4_ net-_u5-pad3_ ] net-_u1-pad5_ u7 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end |