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authorSumanto Kar2025-06-14 17:58:58 +0530
committerGitHub2025-06-14 17:58:58 +0530
commiteaf176100fc3c4eb20dab7f8293fa5d09f3409da (patch)
tree19078474dd4fe389cb4a0496df56d2cf56fe2273 /library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and.sub
parent7975bc597123cab9d82f26262ea23f1e03282422 (diff)
parentfe3e9dcb6f62796ff392d7ec68febbd0a82e318b (diff)
downloadeSim-master.tar.gz
eSim-master.tar.bz2
eSim-master.zip
Merge pull request #363 from Shanthipriya20/masterHEADmaster
Subcircuitfiles Files of ICs (Contributor : Shanthi priya)
Diffstat (limited to 'library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and.sub')
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diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and.sub b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and.sub
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+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and \ No newline at end of file