diff options
| author | Sumanto Kar | 2025-06-14 17:58:58 +0530 |
|---|---|---|
| committer | GitHub | 2025-06-14 17:58:58 +0530 |
| commit | eaf176100fc3c4eb20dab7f8293fa5d09f3409da (patch) | |
| tree | 19078474dd4fe389cb4a0496df56d2cf56fe2273 /library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.sub | |
| parent | 7975bc597123cab9d82f26262ea23f1e03282422 (diff) | |
| parent | fe3e9dcb6f62796ff392d7ec68febbd0a82e318b (diff) | |
| download | eSim-master.tar.gz eSim-master.tar.bz2 eSim-master.zip | |
Subcircuitfiles Files of ICs (Contributor : Shanthi priya)
Diffstat (limited to 'library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.sub')
| -rw-r--r-- | library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.sub | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.sub b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.sub new file mode 100644 index 00000000..e87dde76 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.sub @@ -0,0 +1,36 @@ +* Subcircuit g_origin +.subckt g_origin /w /x /y /z net-_u1-pad5_ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\g_origin\g_origin.cir +.include 4_OR.sub +* u3 /y net-_u3-pad2_ d_inverter +* u4 /z net-_u4-pad2_ d_inverter +x1 net-_u5-pad3_ net-_u6-pad3_ net-_u7-pad3_ net-_u8-pad3_ net-_u1-pad5_ 4_OR +* u2 /x net-_u2-pad2_ d_inverter +* u5 net-_u2-pad2_ /y net-_u5-pad3_ d_and +* u6 /y net-_u4-pad2_ net-_u6-pad3_ d_and +* u7 /x net-_u3-pad2_ net-_u7-pad3_ d_and +* u8 /w net-_u2-pad2_ net-_u8-pad3_ d_and +a1 /y net-_u3-pad2_ u3 +a2 /z net-_u4-pad2_ u4 +a3 /x net-_u2-pad2_ u2 +a4 [net-_u2-pad2_ /y ] net-_u5-pad3_ u5 +a5 [/y net-_u4-pad2_ ] net-_u6-pad3_ u6 +a6 [/x net-_u3-pad2_ ] net-_u7-pad3_ u7 +a7 [/w net-_u2-pad2_ ] net-_u8-pad3_ u8 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends g_origin
\ No newline at end of file |