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| author | Sumanto Kar | 2025-06-14 17:58:58 +0530 |
|---|---|---|
| committer | GitHub | 2025-06-14 17:58:58 +0530 |
| commit | eaf176100fc3c4eb20dab7f8293fa5d09f3409da (patch) | |
| tree | 19078474dd4fe389cb4a0496df56d2cf56fe2273 /library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.sub | |
| parent | 7975bc597123cab9d82f26262ea23f1e03282422 (diff) | |
| parent | fe3e9dcb6f62796ff392d7ec68febbd0a82e318b (diff) | |
| download | eSim-master.tar.gz eSim-master.tar.bz2 eSim-master.zip | |
Subcircuitfiles Files of ICs (Contributor : Shanthi priya)
Diffstat (limited to 'library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.sub')
| -rw-r--r-- | library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.sub | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.sub b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.sub new file mode 100644 index 00000000..7be62924 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.sub @@ -0,0 +1,26 @@ +* Subcircuit e_origin +.subckt e_origin /x /y /z net-_u1-pad4_ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\e_origin\e_origin.cir +* u2 /x net-_u2-pad2_ d_inverter +* u3 /z net-_u3-pad2_ d_inverter +* u4 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad3_ d_and +* u5 /y net-_u3-pad2_ net-_u5-pad3_ d_and +* u6 net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad4_ d_or +a1 /x net-_u2-pad2_ u2 +a2 /z net-_u3-pad2_ u3 +a3 [net-_u2-pad2_ net-_u3-pad2_ ] net-_u4-pad3_ u4 +a4 [/y net-_u3-pad2_ ] net-_u5-pad3_ u5 +a5 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad4_ u6 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends e_origin
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