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| author | Sumanto Kar | 2025-06-14 17:58:58 +0530 |
|---|---|---|
| committer | GitHub | 2025-06-14 17:58:58 +0530 |
| commit | eaf176100fc3c4eb20dab7f8293fa5d09f3409da (patch) | |
| tree | 19078474dd4fe389cb4a0496df56d2cf56fe2273 /library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.cir.out | |
| parent | 7975bc597123cab9d82f26262ea23f1e03282422 (diff) | |
| parent | fe3e9dcb6f62796ff392d7ec68febbd0a82e318b (diff) | |
| download | eSim-master.tar.gz eSim-master.tar.bz2 eSim-master.zip | |
Subcircuitfiles Files of ICs (Contributor : Shanthi priya)
Diffstat (limited to 'library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.cir.out')
| -rw-r--r-- | library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.cir.out | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.cir.out new file mode 100644 index 00000000..6eb3a7d8 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.cir.out @@ -0,0 +1,44 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\c_origin\c_origin.cir + +* u1 /w /x /y /z net-_u1-pad5_ port +* u2 /w net-_u2-pad2_ d_inverter +* u3 /x net-_u3-pad2_ d_inverter +* u4 /y net-_u4-pad2_ d_inverter +* u5 net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad3_ d_and +* u6 net-_u3-pad2_ /z net-_u6-pad3_ d_and +* u7 net-_u2-pad2_ /x net-_u7-pad3_ d_and +* u8 net-_u5-pad3_ net-_u6-pad3_ net-_u8-pad3_ d_or +* u9 net-_u8-pad3_ net-_u7-pad3_ net-_u1-pad5_ d_or +a1 /w net-_u2-pad2_ u2 +a2 /x net-_u3-pad2_ u3 +a3 /y net-_u4-pad2_ u4 +a4 [net-_u3-pad2_ net-_u4-pad2_ ] net-_u5-pad3_ u5 +a5 [net-_u3-pad2_ /z ] net-_u6-pad3_ u6 +a6 [net-_u2-pad2_ /x ] net-_u7-pad3_ u7 +a7 [net-_u5-pad3_ net-_u6-pad3_ ] net-_u8-pad3_ u8 +a8 [net-_u8-pad3_ net-_u7-pad3_ ] net-_u1-pad5_ u9 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u8 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u9 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end |