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| author | Sumanto Kar | 2023-05-04 13:14:46 +0530 |
|---|---|---|
| committer | GitHub | 2023-05-04 13:14:46 +0530 |
| commit | 8c2244ffc20b87256cec11e4f5fbd88fd3348300 (patch) | |
| tree | 9a81f2090740d02ad33b29f5db49123995c0a41e /library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.cir | |
| parent | 732e2c2a1b63b3af1f17a2f1a8c128db2a757b4c (diff) | |
| parent | 57e699fdd79e8be77385bc2a4e017408e5d5afaa (diff) | |
| download | eSim-8c2244ffc20b87256cec11e4f5fbd88fd3348300.tar.gz eSim-8c2244ffc20b87256cec11e4f5fbd88fd3348300.tar.bz2 eSim-8c2244ffc20b87256cec11e4f5fbd88fd3348300.zip | |
Merge pull request #232 from VanshikaTanwar/master
Sub-circuit files for INA106, 74LVC1G19, 74V1G14, Precision Rectifier IC, Log Amplifier IC
Diffstat (limited to 'library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.cir')
| -rw-r--r-- | library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.cir | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.cir b/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.cir new file mode 100644 index 00000000..f945869f --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.cir @@ -0,0 +1,24 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\TINA_TI_Rectifier\TINA_TI_Rectifier.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 9/8/2022 12:13:00 PM + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 ? Net-_C1-Pad1_ /Vin /Vneg ? Net-_C1-Pad2_ /Vpos ? lm_741 +X2 ? Net-_R2-Pad1_ Net-_D2-Pad2_ /Vneg ? /Vout /Vpos ? lm_741 +R1 /Vin GND 49.9 +R3 Net-_D2-Pad2_ GND 1k +D2 Net-_C1-Pad2_ Net-_D2-Pad2_ eSim_Diode +D1 Net-_C1-Pad1_ Net-_C1-Pad2_ eSim_Diode +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 47p +R2 Net-_R2-Pad1_ Net-_C1-Pad1_ 1k +R4 /Vout Net-_R2-Pad1_ 1k +C3 /Vpos GND 100p +C5 /Vpos GND 100n +C2 /Vneg GND 100p +C4 /Vneg GND 100n +U1 /Vin /Vneg /Vout /Vpos PORT + +.end |