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| author | Aditya Minocha | 2024-08-25 21:22:16 +0530 |
|---|---|---|
| committer | GitHub | 2024-08-25 21:22:16 +0530 |
| commit | 4148cefab1bccb6c2cd4ae3606e5450cf090dac0 (patch) | |
| tree | 0253e7f159aedd0d8ceef890219b225db240870c /library/SubcircuitLibrary/SRAM/analysis | |
| parent | 524f8be6ff4b94f38c6df0f2fb1f45170de6b3c6 (diff) | |
| download | eSim-4148cefab1bccb6c2cd4ae3606e5450cf090dac0.tar.gz eSim-4148cefab1bccb6c2cd4ae3606e5450cf090dac0.tar.bz2 eSim-4148cefab1bccb6c2cd4ae3606e5450cf090dac0.zip | |
Static Memory IC - 6T SRAM Cell
Diffstat (limited to 'library/SubcircuitLibrary/SRAM/analysis')
| -rw-r--r-- | library/SubcircuitLibrary/SRAM/analysis | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/SRAM/analysis b/library/SubcircuitLibrary/SRAM/analysis new file mode 100644 index 00000000..e762d6f5 --- /dev/null +++ b/library/SubcircuitLibrary/SRAM/analysis @@ -0,0 +1 @@ +.tran 0.01e-09 80e-09 0e-09
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