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| author | Sumanto Kar | 2024-11-21 21:32:12 +0530 |
|---|---|---|
| committer | Sumanto Kar | 2024-11-21 21:32:12 +0530 |
| commit | 8e6fb624fda240239f9bfff67b40c28fba44e744 (patch) | |
| tree | e0164ce8ed66b4b6d26fb522b37daed7d3d14dde /library/SubcircuitLibrary/SN74LS138 | |
| parent | 5338d6a340e0fb746bcfa9b6184ee884c45ff44b (diff) | |
| download | eSim-8e6fb624fda240239f9bfff67b40c28fba44e744.tar.gz eSim-8e6fb624fda240239f9bfff67b40c28fba44e744.tar.bz2 eSim-8e6fb624fda240239f9bfff67b40c28fba44e744.zip | |
SN74LS138 is a 3-to-8 line decoder/demultiplexer
Diffstat (limited to 'library/SubcircuitLibrary/SN74LS138')
24 files changed, 1693 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/SN74LS138/3_and-cache.lib b/library/SubcircuitLibrary/SN74LS138/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS138/3_and.cir b/library/SubcircuitLibrary/SN74LS138/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LS138/3_and.cir.out b/library/SubcircuitLibrary/SN74LS138/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS138/3_and.pro b/library/SubcircuitLibrary/SN74LS138/3_and.pro new file mode 100644 index 00000000..00597a5a --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN74LS138/3_and.sch b/library/SubcircuitLibrary/SN74LS138/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS138/3_and.sub b/library/SubcircuitLibrary/SN74LS138/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS138/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS138/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS138/4_and-cache.lib b/library/SubcircuitLibrary/SN74LS138/4_and-cache.lib new file mode 100644 index 00000000..60f1a83d --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS138/4_and-rescue.lib b/library/SubcircuitLibrary/SN74LS138/4_and-rescue.lib new file mode 100644 index 00000000..e3833051 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/4_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS138/4_and.cir b/library/SubcircuitLibrary/SN74LS138/4_and.cir new file mode 100644 index 00000000..fdf2e107 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LS138/4_and.cir.out b/library/SubcircuitLibrary/SN74LS138/4_and.cir.out new file mode 100644 index 00000000..f40e5bc6 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS138/4_and.pro b/library/SubcircuitLibrary/SN74LS138/4_and.pro new file mode 100644 index 00000000..b13a0a82 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/4_and.pro @@ -0,0 +1,57 @@ +update=Wed Mar 18 19:54:24 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=4_and-rescue +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/library/SubcircuitLibrary/SN74LS138/4_and.sch b/library/SubcircuitLibrary/SN74LS138/4_and.sch new file mode 100644 index 00000000..f5e8febd --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/4_and.sch @@ -0,0 +1,151 @@ +EESchema Schematic File Version 2 +LIBS:4_and-rescue +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-4_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +Text Notes 3450 2650 0 60 ~ 12 +in1 +Text Notes 3450 2950 0 60 ~ 12 +in2 +Text Notes 3500 3300 0 60 ~ 12 +in3 +Text Notes 3500 3550 0 60 ~ 12 +in4 +Text Notes 6150 3350 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS138/4_and.sub b/library/SubcircuitLibrary/SN74LS138/4_and.sub new file mode 100644 index 00000000..8663f37e --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS138/4_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS138/4_and_Previous_Values.xml new file mode 100644 index 00000000..f2ba0130 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/4_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS138/SN74LS138-cache.lib b/library/SubcircuitLibrary/SN74LS138/SN74LS138-cache.lib new file mode 100644 index 00000000..7a756fd1 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/SN74LS138-cache.lib @@ -0,0 +1,95 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS138/SN74LS138.cir b/library/SubcircuitLibrary/SN74LS138/SN74LS138.cir new file mode 100644 index 00000000..9024ca93 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/SN74LS138.cir @@ -0,0 +1,38 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN74LS138\SN74LS138.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/18/24 15:20:33 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X2 Net-_U13-Pad2_ Net-_U14-Pad2_ Net-_U15-Pad2_ Net-_X1-Pad4_ Net-_U19-Pad1_ 4_and +U19 Net-_U19-Pad1_ Net-_U1-Pad7_ d_inverter +X3 Net-_U16-Pad2_ Net-_U14-Pad2_ Net-_U15-Pad2_ Net-_X1-Pad4_ Net-_U20-Pad1_ 4_and +U20 Net-_U20-Pad1_ Net-_U1-Pad8_ d_inverter +X4 Net-_U13-Pad2_ Net-_U17-Pad2_ Net-_U15-Pad2_ Net-_X1-Pad4_ Net-_U21-Pad1_ 4_and +U21 Net-_U21-Pad1_ Net-_U1-Pad9_ d_inverter +X5 Net-_U16-Pad2_ Net-_U17-Pad2_ Net-_U15-Pad2_ Net-_X1-Pad4_ Net-_U22-Pad1_ 4_and +U22 Net-_U22-Pad1_ Net-_U1-Pad10_ d_inverter +X6 Net-_U13-Pad2_ Net-_U14-Pad2_ Net-_U18-Pad2_ Net-_X1-Pad4_ Net-_U23-Pad1_ 4_and +U23 Net-_U23-Pad1_ Net-_U1-Pad11_ d_inverter +X7 Net-_U14-Pad2_ Net-_U18-Pad2_ Net-_U16-Pad2_ Net-_X1-Pad4_ Net-_U24-Pad1_ 4_and +U24 Net-_U24-Pad1_ Net-_U1-Pad12_ d_inverter +X8 Net-_U13-Pad2_ Net-_U18-Pad2_ Net-_U17-Pad2_ Net-_X1-Pad4_ Net-_U25-Pad1_ 4_and +U25 Net-_U25-Pad1_ Net-_U1-Pad13_ d_inverter +X9 Net-_X1-Pad4_ Net-_U17-Pad2_ Net-_U16-Pad2_ Net-_U18-Pad2_ Net-_U26-Pad1_ 4_and +U26 Net-_U26-Pad1_ Net-_U1-Pad14_ d_inverter +U18 Net-_U15-Pad2_ Net-_U18-Pad2_ d_inverter +U17 Net-_U14-Pad2_ Net-_U17-Pad2_ d_inverter +U16 Net-_U13-Pad2_ Net-_U16-Pad2_ d_inverter +X1 Net-_U10-Pad2_ Net-_U11-Pad2_ Net-_U12-Pad2_ Net-_X1-Pad4_ 3_and +U8 Net-_U1-Pad1_ Net-_U10-Pad1_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U11 Net-_U1-Pad2_ Net-_U11-Pad2_ d_inverter +U12 Net-_U1-Pad3_ Net-_U12-Pad2_ d_inverter +U13 Net-_U1-Pad4_ Net-_U13-Pad2_ d_inverter +U14 Net-_U1-Pad5_ Net-_U14-Pad2_ d_inverter +U15 Net-_U1-Pad6_ Net-_U15-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LS138/SN74LS138.cir.out b/library/SubcircuitLibrary/SN74LS138/SN74LS138.cir.out new file mode 100644 index 00000000..4ffe8f81 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/SN74LS138.cir.out @@ -0,0 +1,95 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn74ls138\sn74ls138.cir + +.include 3_and.sub +.include 4_and.sub +x2 net-_u13-pad2_ net-_u14-pad2_ net-_u15-pad2_ net-_x1-pad4_ net-_u19-pad1_ 4_and +* u19 net-_u19-pad1_ net-_u1-pad7_ d_inverter +x3 net-_u16-pad2_ net-_u14-pad2_ net-_u15-pad2_ net-_x1-pad4_ net-_u20-pad1_ 4_and +* u20 net-_u20-pad1_ net-_u1-pad8_ d_inverter +x4 net-_u13-pad2_ net-_u17-pad2_ net-_u15-pad2_ net-_x1-pad4_ net-_u21-pad1_ 4_and +* u21 net-_u21-pad1_ net-_u1-pad9_ d_inverter +x5 net-_u16-pad2_ net-_u17-pad2_ net-_u15-pad2_ net-_x1-pad4_ net-_u22-pad1_ 4_and +* u22 net-_u22-pad1_ net-_u1-pad10_ d_inverter +x6 net-_u13-pad2_ net-_u14-pad2_ net-_u18-pad2_ net-_x1-pad4_ net-_u23-pad1_ 4_and +* u23 net-_u23-pad1_ net-_u1-pad11_ d_inverter +x7 net-_u14-pad2_ net-_u18-pad2_ net-_u16-pad2_ net-_x1-pad4_ net-_u24-pad1_ 4_and +* u24 net-_u24-pad1_ net-_u1-pad12_ d_inverter +x8 net-_u13-pad2_ net-_u18-pad2_ net-_u17-pad2_ net-_x1-pad4_ net-_u25-pad1_ 4_and +* u25 net-_u25-pad1_ net-_u1-pad13_ d_inverter +x9 net-_x1-pad4_ net-_u17-pad2_ net-_u16-pad2_ net-_u18-pad2_ net-_u26-pad1_ 4_and +* u26 net-_u26-pad1_ net-_u1-pad14_ d_inverter +* u18 net-_u15-pad2_ net-_u18-pad2_ d_inverter +* u17 net-_u14-pad2_ net-_u17-pad2_ d_inverter +* u16 net-_u13-pad2_ net-_u16-pad2_ d_inverter +x1 net-_u10-pad2_ net-_u11-pad2_ net-_u12-pad2_ net-_x1-pad4_ 3_and +* u8 net-_u1-pad1_ net-_u10-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u11 net-_u1-pad2_ net-_u11-pad2_ d_inverter +* u12 net-_u1-pad3_ net-_u12-pad2_ d_inverter +* u13 net-_u1-pad4_ net-_u13-pad2_ d_inverter +* u14 net-_u1-pad5_ net-_u14-pad2_ d_inverter +* u15 net-_u1-pad6_ net-_u15-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +a1 net-_u19-pad1_ net-_u1-pad7_ u19 +a2 net-_u20-pad1_ net-_u1-pad8_ u20 +a3 net-_u21-pad1_ net-_u1-pad9_ u21 +a4 net-_u22-pad1_ net-_u1-pad10_ u22 +a5 net-_u23-pad1_ net-_u1-pad11_ u23 +a6 net-_u24-pad1_ net-_u1-pad12_ u24 +a7 net-_u25-pad1_ net-_u1-pad13_ u25 +a8 net-_u26-pad1_ net-_u1-pad14_ u26 +a9 net-_u15-pad2_ net-_u18-pad2_ u18 +a10 net-_u14-pad2_ net-_u17-pad2_ u17 +a11 net-_u13-pad2_ net-_u16-pad2_ u16 +a12 net-_u1-pad1_ net-_u10-pad1_ u8 +a13 net-_u10-pad1_ net-_u10-pad2_ u10 +a14 net-_u1-pad2_ net-_u11-pad2_ u11 +a15 net-_u1-pad3_ net-_u12-pad2_ u12 +a16 net-_u1-pad4_ net-_u13-pad2_ u13 +a17 net-_u1-pad5_ net-_u14-pad2_ u14 +a18 net-_u1-pad6_ net-_u15-pad2_ u15 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-03 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS138/SN74LS138.pro b/library/SubcircuitLibrary/SN74LS138/SN74LS138.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/SN74LS138.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74LS138/SN74LS138.proj b/library/SubcircuitLibrary/SN74LS138/SN74LS138.proj new file mode 100644 index 00000000..7b1a94a1 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/SN74LS138.proj @@ -0,0 +1 @@ +schematicFile New.sch diff --git a/library/SubcircuitLibrary/SN74LS138/SN74LS138.sch b/library/SubcircuitLibrary/SN74LS138/SN74LS138.sch new file mode 100644 index 00000000..37a20de9 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/SN74LS138.sch @@ -0,0 +1,665 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN74LS138-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 4_and X2 +U 1 1 665D7644 +P 12650 5550 +F 0 "X2" H 12700 5500 60 0000 C CNN +F 1 "4_and" H 12750 5650 60 0000 C CNN +F 2 "" H 12650 5550 60 0000 C CNN +F 3 "" H 12650 5550 60 0000 C CNN + 1 12650 5550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U19 +U 1 1 665D77DD +P 13450 5550 +F 0 "U19" H 13450 5450 60 0000 C CNN +F 1 "d_inverter" H 13450 5700 60 0000 C CNN +F 2 "" H 13500 5500 60 0000 C CNN +F 3 "" H 13500 5500 60 0000 C CNN + 1 13450 5550 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X3 +U 1 1 665D79AA +P 12650 6050 +F 0 "X3" H 12700 6000 60 0000 C CNN +F 1 "4_and" H 12750 6150 60 0000 C CNN +F 2 "" H 12650 6050 60 0000 C CNN +F 3 "" H 12650 6050 60 0000 C CNN + 1 12650 6050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U20 +U 1 1 665D79B0 +P 13450 6050 +F 0 "U20" H 13450 5950 60 0000 C CNN +F 1 "d_inverter" H 13450 6200 60 0000 C CNN +F 2 "" H 13500 6000 60 0000 C CNN +F 3 "" H 13500 6000 60 0000 C CNN + 1 13450 6050 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X4 +U 1 1 665D7B32 +P 12650 6550 +F 0 "X4" H 12700 6500 60 0000 C CNN +F 1 "4_and" H 12750 6650 60 0000 C CNN +F 2 "" H 12650 6550 60 0000 C CNN +F 3 "" H 12650 6550 60 0000 C CNN + 1 12650 6550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U21 +U 1 1 665D7B38 +P 13450 6550 +F 0 "U21" H 13450 6450 60 0000 C CNN +F 1 "d_inverter" H 13450 6700 60 0000 C CNN +F 2 "" H 13500 6500 60 0000 C CNN +F 3 "" H 13500 6500 60 0000 C CNN + 1 13450 6550 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X5 +U 1 1 665D7B3E +P 12650 7050 +F 0 "X5" H 12700 7000 60 0000 C CNN +F 1 "4_and" H 12750 7150 60 0000 C CNN +F 2 "" H 12650 7050 60 0000 C CNN +F 3 "" H 12650 7050 60 0000 C CNN + 1 12650 7050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U22 +U 1 1 665D7B44 +P 13450 7050 +F 0 "U22" H 13450 6950 60 0000 C CNN +F 1 "d_inverter" H 13450 7200 60 0000 C CNN +F 2 "" H 13500 7000 60 0000 C CNN +F 3 "" H 13500 7000 60 0000 C CNN + 1 13450 7050 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X6 +U 1 1 665D7ED8 +P 12650 7550 +F 0 "X6" H 12700 7500 60 0000 C CNN +F 1 "4_and" H 12750 7650 60 0000 C CNN +F 2 "" H 12650 7550 60 0000 C CNN +F 3 "" H 12650 7550 60 0000 C CNN + 1 12650 7550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U23 +U 1 1 665D7EDE +P 13450 7550 +F 0 "U23" H 13450 7450 60 0000 C CNN +F 1 "d_inverter" H 13450 7700 60 0000 C CNN +F 2 "" H 13500 7500 60 0000 C CNN +F 3 "" H 13500 7500 60 0000 C CNN + 1 13450 7550 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X7 +U 1 1 665D7EE4 +P 12650 8050 +F 0 "X7" H 12700 8000 60 0000 C CNN +F 1 "4_and" H 12750 8150 60 0000 C CNN +F 2 "" H 12650 8050 60 0000 C CNN +F 3 "" H 12650 8050 60 0000 C CNN + 1 12650 8050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U24 +U 1 1 665D7EEA +P 13450 8050 +F 0 "U24" H 13450 7950 60 0000 C CNN +F 1 "d_inverter" H 13450 8200 60 0000 C CNN +F 2 "" H 13500 8000 60 0000 C CNN +F 3 "" H 13500 8000 60 0000 C CNN + 1 13450 8050 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X8 +U 1 1 665D7EF0 +P 12650 8550 +F 0 "X8" H 12700 8500 60 0000 C CNN +F 1 "4_and" H 12750 8650 60 0000 C CNN +F 2 "" H 12650 8550 60 0000 C CNN +F 3 "" H 12650 8550 60 0000 C CNN + 1 12650 8550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U25 +U 1 1 665D7EF6 +P 13450 8550 +F 0 "U25" H 13450 8450 60 0000 C CNN +F 1 "d_inverter" H 13450 8700 60 0000 C CNN +F 2 "" H 13500 8500 60 0000 C CNN +F 3 "" H 13500 8500 60 0000 C CNN + 1 13450 8550 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X9 +U 1 1 665D7EFC +P 12650 9050 +F 0 "X9" H 12700 9000 60 0000 C CNN +F 1 "4_and" H 12750 9150 60 0000 C CNN +F 2 "" H 12650 9050 60 0000 C CNN +F 3 "" H 12650 9050 60 0000 C CNN + 1 12650 9050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U26 +U 1 1 665D7F02 +P 13450 9050 +F 0 "U26" H 13450 8950 60 0000 C CNN +F 1 "d_inverter" H 13450 9200 60 0000 C CNN +F 2 "" H 13500 9000 60 0000 C CNN +F 3 "" H 13500 9000 60 0000 C CNN + 1 13450 9050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U18 +U 1 1 665D879A +P 10400 9200 +F 0 "U18" H 10400 9100 60 0000 C CNN +F 1 "d_inverter" H 10400 9350 60 0000 C CNN +F 2 "" H 10450 9150 60 0000 C CNN +F 3 "" H 10450 9150 60 0000 C CNN + 1 10400 9200 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U17 +U 1 1 665D8853 +P 10400 8600 +F 0 "U17" H 10400 8500 60 0000 C CNN +F 1 "d_inverter" H 10400 8750 60 0000 C CNN +F 2 "" H 10450 8550 60 0000 C CNN +F 3 "" H 10450 8550 60 0000 C CNN + 1 10400 8600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U16 +U 1 1 665D88B9 +P 10400 8100 +F 0 "U16" H 10400 8000 60 0000 C CNN +F 1 "d_inverter" H 10400 8250 60 0000 C CNN +F 2 "" H 10450 8050 60 0000 C CNN +F 3 "" H 10450 8050 60 0000 C CNN + 1 10400 8100 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X1 +U 1 1 665D95DE +P 8550 6750 +F 0 "X1" H 8650 6700 60 0000 C CNN +F 1 "3_and" H 8700 6900 60 0000 C CNN +F 2 "" H 8550 6750 60 0000 C CNN +F 3 "" H 8550 6750 60 0000 C CNN + 1 8550 6750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 665D96C5 +P 7050 6600 +F 0 "U8" H 7050 6500 60 0000 C CNN +F 1 "d_inverter" H 7050 6750 60 0000 C CNN +F 2 "" H 7100 6550 60 0000 C CNN +F 3 "" H 7100 6550 60 0000 C CNN + 1 7050 6600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U10 +U 1 1 665D979E +P 7900 6600 +F 0 "U10" H 7650 6900 60 0000 C CNN +F 1 "d_inverter" H 7950 6900 60 0000 C CNN +F 2 "" H 7950 6550 60 0000 C CNN +F 3 "" H 7950 6550 60 0000 C CNN + 1 7900 6600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U11 +U 1 1 665D981E +P 7900 6700 +F 0 "U11" H 7650 7000 60 0000 C CNN +F 1 "d_inverter" H 7950 7000 60 0000 C CNN +F 2 "" H 7950 6650 60 0000 C CNN +F 3 "" H 7950 6650 60 0000 C CNN + 1 7900 6700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U12 +U 1 1 665D9873 +P 7900 6800 +F 0 "U12" H 7650 7100 60 0000 C CNN +F 1 "d_inverter" H 7950 7100 60 0000 C CNN +F 2 "" H 7950 6750 60 0000 C CNN +F 3 "" H 7950 6750 60 0000 C CNN + 1 7900 6800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U13 +U 1 1 665D9DBA +P 9200 8100 +F 0 "U13" H 9200 8000 60 0000 C CNN +F 1 "d_inverter" H 9200 8250 60 0000 C CNN +F 2 "" H 9250 8050 60 0000 C CNN +F 3 "" H 9250 8050 60 0000 C CNN + 1 9200 8100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U14 +U 1 1 665D9E3F +P 9200 8600 +F 0 "U14" H 9200 8500 60 0000 C CNN +F 1 "d_inverter" H 9200 8750 60 0000 C CNN +F 2 "" H 9250 8550 60 0000 C CNN +F 3 "" H 9250 8550 60 0000 C CNN + 1 9200 8600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U15 +U 1 1 665D9EAF +P 9200 9200 +F 0 "U15" H 9200 9100 60 0000 C CNN +F 1 "d_inverter" H 9200 9350 60 0000 C CNN +F 2 "" H 9250 9150 60 0000 C CNN +F 3 "" H 9250 9150 60 0000 C CNN + 1 9200 9200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 12250 5400 9500 5400 +Wire Wire Line + 9500 5400 9500 8400 +Wire Wire Line + 9500 8400 12250 8400 +Wire Wire Line + 12250 5700 12050 5700 +Wire Wire Line + 12050 5700 12050 8900 +Wire Wire Line + 12250 8200 12050 8200 +Connection ~ 12050 8200 +Wire Wire Line + 12250 7700 12050 7700 +Connection ~ 12050 7700 +Wire Wire Line + 12250 8700 12050 8700 +Connection ~ 12050 8700 +Wire Wire Line + 12250 7200 12050 7200 +Connection ~ 12050 7200 +Wire Wire Line + 9050 6700 12250 6700 +Connection ~ 12050 6700 +Wire Wire Line + 12250 6200 12050 6200 +Connection ~ 12050 6200 +Wire Wire Line + 10750 9100 12250 9100 +Wire Wire Line + 10750 5900 10750 9100 +Wire Wire Line + 10750 5900 12250 5900 +Wire Wire Line + 9500 9200 10100 9200 +Wire Wire Line + 9900 5600 9900 9200 +Wire Wire Line + 9900 5600 12250 5600 +Wire Wire Line + 12250 5500 9650 5500 +Wire Wire Line + 9650 5500 9650 8600 +Wire Wire Line + 9500 8600 10100 8600 +Wire Wire Line + 10100 8100 9500 8100 +Connection ~ 9500 8100 +Wire Wire Line + 10700 8600 12250 8600 +Wire Wire Line + 10700 8100 12250 8100 +Wire Wire Line + 12250 6000 9650 6000 +Connection ~ 9650 6000 +Wire Wire Line + 12250 6100 9900 6100 +Connection ~ 9900 6100 +Wire Wire Line + 12250 6400 9500 6400 +Connection ~ 9500 6400 +Wire Wire Line + 12250 6500 11050 6500 +Wire Wire Line + 11050 6500 11050 9000 +Wire Wire Line + 11050 7000 12250 7000 +Wire Wire Line + 12250 6900 10750 6900 +Connection ~ 10750 6900 +Wire Wire Line + 12250 6600 9900 6600 +Connection ~ 9900 6600 +Wire Wire Line + 12250 7100 9900 7100 +Connection ~ 9900 7100 +Wire Wire Line + 12250 7400 9500 7400 +Connection ~ 9500 7400 +Wire Wire Line + 12250 7500 9650 7500 +Connection ~ 9650 7500 +Wire Wire Line + 12250 7600 11600 7600 +Wire Wire Line + 11600 7600 11600 9200 +Wire Wire Line + 11600 8000 12250 8000 +Wire Wire Line + 12250 7900 9650 7900 +Connection ~ 9650 7900 +Wire Wire Line + 11600 8500 12250 8500 +Connection ~ 11600 8000 +Wire Wire Line + 12050 8900 12250 8900 +Connection ~ 12050 8900 +Wire Wire Line + 10700 9200 12250 9200 +Connection ~ 11600 9200 +Connection ~ 11600 8500 +Connection ~ 11050 8600 +Connection ~ 11050 7000 +Wire Wire Line + 11050 9000 12250 9000 +Connection ~ 10750 8100 +Wire Wire Line + 7350 6600 7600 6600 +Connection ~ 9650 8600 +Wire Wire Line + 6750 6700 7600 6700 +Wire Wire Line + 7600 6800 6750 6800 +Wire Wire Line + 14400 6950 14400 5550 +Wire Wire Line + 14400 5550 13750 5550 +Wire Wire Line + 13750 6050 14250 6050 +Wire Wire Line + 14250 6050 14250 7050 +Wire Wire Line + 14250 7050 14400 7050 +Wire Wire Line + 13750 6550 14100 6550 +Wire Wire Line + 14100 6550 14100 7150 +Wire Wire Line + 14100 7150 14400 7150 +Wire Wire Line + 14400 7250 13750 7250 +Wire Wire Line + 13750 7250 13750 7050 +Wire Wire Line + 13750 7350 13750 7550 +Wire Wire Line + 13750 7350 14400 7350 +Wire Wire Line + 14400 7450 13850 7450 +Wire Wire Line + 13850 7450 13850 8050 +Wire Wire Line + 13850 8050 13750 8050 +Wire Wire Line + 13750 8550 14000 8550 +Wire Wire Line + 14000 8550 14000 7550 +Wire Wire Line + 14000 7550 14400 7550 +Wire Wire Line + 14400 7650 14200 7650 +Wire Wire Line + 14200 7650 14200 9050 +Wire Wire Line + 14200 9050 13750 9050 +Connection ~ 9900 9200 +$Comp +L PORT U1 +U 7 1 665D9B14 +P 14650 6950 +F 0 "U1" H 14700 7050 30 0000 C CNN +F 1 "PORT" H 14650 6950 30 0000 C CNN +F 2 "" H 14650 6950 60 0000 C CNN +F 3 "" H 14650 6950 60 0000 C CNN + 7 14650 6950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 665D9CEE +P 14650 7050 +F 0 "U1" H 14700 7150 30 0000 C CNN +F 1 "PORT" H 14650 7050 30 0000 C CNN +F 2 "" H 14650 7050 60 0000 C CNN +F 3 "" H 14650 7050 60 0000 C CNN + 8 14650 7050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 665D9D71 +P 14650 7150 +F 0 "U1" H 14700 7250 30 0000 C CNN +F 1 "PORT" H 14650 7150 30 0000 C CNN +F 2 "" H 14650 7150 60 0000 C CNN +F 3 "" H 14650 7150 60 0000 C CNN + 9 14650 7150 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 665D9DE6 +P 14650 7250 +F 0 "U1" H 14700 7350 30 0000 C CNN +F 1 "PORT" H 14650 7250 30 0000 C CNN +F 2 "" H 14650 7250 60 0000 C CNN +F 3 "" H 14650 7250 60 0000 C CNN + 10 14650 7250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 665D9E5B +P 14650 7350 +F 0 "U1" H 14700 7450 30 0000 C CNN +F 1 "PORT" H 14650 7350 30 0000 C CNN +F 2 "" H 14650 7350 60 0000 C CNN +F 3 "" H 14650 7350 60 0000 C CNN + 11 14650 7350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 665D9ED2 +P 14650 7450 +F 0 "U1" H 14700 7550 30 0000 C CNN +F 1 "PORT" H 14650 7450 30 0000 C CNN +F 2 "" H 14650 7450 60 0000 C CNN +F 3 "" H 14650 7450 60 0000 C CNN + 12 14650 7450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 665D9F4B +P 14650 7550 +F 0 "U1" H 14700 7650 30 0000 C CNN +F 1 "PORT" H 14650 7550 30 0000 C CNN +F 2 "" H 14650 7550 60 0000 C CNN +F 3 "" H 14650 7550 60 0000 C CNN + 13 14650 7550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 665D9FC6 +P 14650 7650 +F 0 "U1" H 14700 7750 30 0000 C CNN +F 1 "PORT" H 14650 7650 30 0000 C CNN +F 2 "" H 14650 7650 60 0000 C CNN +F 3 "" H 14650 7650 60 0000 C CNN + 14 14650 7650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 665DB37C +P 6500 6600 +F 0 "U1" H 6550 6700 30 0000 C CNN +F 1 "PORT" H 6500 6600 30 0000 C CNN +F 2 "" H 6500 6600 60 0000 C CNN +F 3 "" H 6500 6600 60 0000 C CNN + 1 6500 6600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 665DB3FD +P 6500 6700 +F 0 "U1" H 6550 6800 30 0000 C CNN +F 1 "PORT" H 6500 6700 30 0000 C CNN +F 2 "" H 6500 6700 60 0000 C CNN +F 3 "" H 6500 6700 60 0000 C CNN + 2 6500 6700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 665DB46C +P 6500 6800 +F 0 "U1" H 6550 6900 30 0000 C CNN +F 1 "PORT" H 6500 6800 30 0000 C CNN +F 2 "" H 6500 6800 60 0000 C CNN +F 3 "" H 6500 6800 60 0000 C CNN + 3 6500 6800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 665DB971 +P 8650 8100 +F 0 "U1" H 8700 8200 30 0000 C CNN +F 1 "PORT" H 8650 8100 30 0000 C CNN +F 2 "" H 8650 8100 60 0000 C CNN +F 3 "" H 8650 8100 60 0000 C CNN + 4 8650 8100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 665DB9EA +P 8650 8600 +F 0 "U1" H 8700 8700 30 0000 C CNN +F 1 "PORT" H 8650 8600 30 0000 C CNN +F 2 "" H 8650 8600 60 0000 C CNN +F 3 "" H 8650 8600 60 0000 C CNN + 5 8650 8600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 665DBA59 +P 8650 9200 +F 0 "U1" H 8700 9300 30 0000 C CNN +F 1 "PORT" H 8650 9200 30 0000 C CNN +F 2 "" H 8650 9200 60 0000 C CNN +F 3 "" H 8650 9200 60 0000 C CNN + 6 8650 9200 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS138/SN74LS138.sub b/library/SubcircuitLibrary/SN74LS138/SN74LS138.sub new file mode 100644 index 00000000..58836a60 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/SN74LS138.sub @@ -0,0 +1,89 @@ +* Subcircuit SN74LS138 +.subckt SN74LS138 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\fossee\esim\library\subcircuitlibrary\sn74ls138\sn74ls138.cir +.include 3_and.sub +.include 4_and.sub +x2 net-_u13-pad2_ net-_u14-pad2_ net-_u15-pad2_ net-_x1-pad4_ net-_u19-pad1_ 4_and +* u19 net-_u19-pad1_ net-_u1-pad7_ d_inverter +x3 net-_u16-pad2_ net-_u14-pad2_ net-_u15-pad2_ net-_x1-pad4_ net-_u20-pad1_ 4_and +* u20 net-_u20-pad1_ net-_u1-pad8_ d_inverter +x4 net-_u13-pad2_ net-_u17-pad2_ net-_u15-pad2_ net-_x1-pad4_ net-_u21-pad1_ 4_and +* u21 net-_u21-pad1_ net-_u1-pad9_ d_inverter +x5 net-_u16-pad2_ net-_u17-pad2_ net-_u15-pad2_ net-_x1-pad4_ net-_u22-pad1_ 4_and +* u22 net-_u22-pad1_ net-_u1-pad10_ d_inverter +x6 net-_u13-pad2_ net-_u14-pad2_ net-_u18-pad2_ net-_x1-pad4_ net-_u23-pad1_ 4_and +* u23 net-_u23-pad1_ net-_u1-pad11_ d_inverter +x7 net-_u14-pad2_ net-_u18-pad2_ net-_u16-pad2_ net-_x1-pad4_ net-_u24-pad1_ 4_and +* u24 net-_u24-pad1_ net-_u1-pad12_ d_inverter +x8 net-_u13-pad2_ net-_u18-pad2_ net-_u17-pad2_ net-_x1-pad4_ net-_u25-pad1_ 4_and +* u25 net-_u25-pad1_ net-_u1-pad13_ d_inverter +x9 net-_x1-pad4_ net-_u17-pad2_ net-_u16-pad2_ net-_u18-pad2_ net-_u26-pad1_ 4_and +* u26 net-_u26-pad1_ net-_u1-pad14_ d_inverter +* u18 net-_u15-pad2_ net-_u18-pad2_ d_inverter +* u17 net-_u14-pad2_ net-_u17-pad2_ d_inverter +* u16 net-_u13-pad2_ net-_u16-pad2_ d_inverter +x1 net-_u10-pad2_ net-_u11-pad2_ net-_u12-pad2_ net-_x1-pad4_ 3_and +* u8 net-_u1-pad1_ net-_u10-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u11 net-_u1-pad2_ net-_u11-pad2_ d_inverter +* u12 net-_u1-pad3_ net-_u12-pad2_ d_inverter +* u13 net-_u1-pad4_ net-_u13-pad2_ d_inverter +* u14 net-_u1-pad5_ net-_u14-pad2_ d_inverter +* u15 net-_u1-pad6_ net-_u15-pad2_ d_inverter +a1 net-_u19-pad1_ net-_u1-pad7_ u19 +a2 net-_u20-pad1_ net-_u1-pad8_ u20 +a3 net-_u21-pad1_ net-_u1-pad9_ u21 +a4 net-_u22-pad1_ net-_u1-pad10_ u22 +a5 net-_u23-pad1_ net-_u1-pad11_ u23 +a6 net-_u24-pad1_ net-_u1-pad12_ u24 +a7 net-_u25-pad1_ net-_u1-pad13_ u25 +a8 net-_u26-pad1_ net-_u1-pad14_ u26 +a9 net-_u15-pad2_ net-_u18-pad2_ u18 +a10 net-_u14-pad2_ net-_u17-pad2_ u17 +a11 net-_u13-pad2_ net-_u16-pad2_ u16 +a12 net-_u1-pad1_ net-_u10-pad1_ u8 +a13 net-_u10-pad1_ net-_u10-pad2_ u10 +a14 net-_u1-pad2_ net-_u11-pad2_ u11 +a15 net-_u1-pad3_ net-_u12-pad2_ u12 +a16 net-_u1-pad4_ net-_u13-pad2_ u13 +a17 net-_u1-pad5_ net-_u14-pad2_ u14 +a18 net-_u1-pad6_ net-_u15-pad2_ u15 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN74LS138
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS138/SN74LS138_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS138/SN74LS138_Previous_Values.xml new file mode 100644 index 00000000..6947b376 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/SN74LS138_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">5</field1></v1><v2 name="Source type">dc<field1 name="Value">0</field1></v2><v4 name="Source type">dc<field1 name="Value">0</field1></v4><v3 name="Source type">dc<field1 name="Value">0</field1></v3><v5 name="Source type">dc<field1 name="Value">0</field1></v5><v6 name="Source type">dc<field1 name="Value">0</field1></v6></source><model><u19 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u19><u20 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u21><u22 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u22><u23 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u23><u24 name="type">d_inverter<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u24><u25 name="type">d_inverter<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u25><u26 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u26><u18 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u18><u17 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u17><u16 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u16><u8 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u8><u10 name="type">d_inverter<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u10><u11 name="type">d_inverter<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_inverter<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_inverter<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u14><u15 name="type">d_inverter<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u15><u7 name="type">adc_bridge<field55 name="Enter value for in_low (default=1.0)" /><field56 name="Enter value for in_high (default=2.0)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /><field58 name="Enter Fall Delay (default=1.0e-9)" /></u7><u9 name="type">adc_bridge<field59 name="Enter value for in_low (default=1.0)" /><field60 name="Enter value for in_high (default=2.0)" /><field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /></u9><u27 name="type">dac_bridge<field63 name="Enter value for out_low (default=0.0)" /><field64 name="Enter value for out_high (default=5.0)" /><field65 name="Enter value for out_undef (default=0.5)" /><field66 name="Enter value for input load (default=1.0e-12)" /><field67 name="Enter the Rise Time (default=1.0e-9)" /><field68 name="Enter the Fall Time (default=1.0e-9)" /></u27></model><devicemodel /><subcircuit><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x2><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x3><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x4><x5><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x5><x6><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x6><x7><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x7><x8><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x8><x9><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x9><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS138/analysis b/library/SubcircuitLibrary/SN74LS138/analysis new file mode 100644 index 00000000..cf94dd7f --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/analysis @@ -0,0 +1 @@ +.tran 0e-03 0e-00 0e-00
\ No newline at end of file |