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authorSumanto Kar2025-02-23 17:37:05 +0530
committerGitHub2025-02-23 17:37:05 +0530
commit311d0244d6093ebdccee00d072016b7a7a1c9372 (patch)
tree02f10e99abea8736d02fc46a12895bcad2743cf6 /library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.sub
parentae99d42b8d2ffeaf91f96d5ffbe5efe91214cf0c (diff)
parent053d7b4f66655f04b4965b26ffea0125cab1ccdd (diff)
downloadeSim-311d0244d6093ebdccee00d072016b7a7a1c9372.tar.gz
eSim-311d0244d6093ebdccee00d072016b7a7a1c9372.tar.bz2
eSim-311d0244d6093ebdccee00d072016b7a7a1c9372.zip
Merge pull request #300 from Maanit491/master
Subcircuit files for different ICs
Diffstat (limited to 'library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.sub')
-rw-r--r--library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.sub18
1 files changed, 18 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.sub b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.sub
new file mode 100644
index 00000000..1a1d27ee
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.sub
@@ -0,0 +1,18 @@
+* Subcircuit NAND_GATE_FINAL
+.subckt NAND_GATE_FINAL net-_q1-pad3_ net-_q2-pad3_ net-_d1-pad2_ net-_r1-pad1_
+* c:\fossee\esim\library\subcircuitlibrary\nand_gate_final\nand_gate_final.cir
+.include D.lib
+.include NPN.lib
+q2 net-_q1-pad1_ net-_q1-pad2_ net-_q2-pad3_ Q2N2222
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222
+r1 net-_r1-pad1_ net-_q1-pad2_ 4k
+r2 net-_r1-pad1_ net-_q3-pad1_ 1.6k
+r4 net-_q4-pad1_ net-_r1-pad1_ 130
+q4 net-_q4-pad1_ net-_q3-pad1_ net-_d1-pad1_ Q2N2222
+q3 net-_q3-pad1_ net-_q1-pad1_ net-_q3-pad3_ Q2N2222
+d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148
+q5 net-_d1-pad2_ net-_q3-pad3_ gnd Q2N2222
+r3 net-_q3-pad3_ gnd 1k
+* Control Statements
+
+.ends NAND_GATE_FINAL \ No newline at end of file