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| author | Sumanto Kar | 2025-02-23 17:37:05 +0530 |
|---|---|---|
| committer | GitHub | 2025-02-23 17:37:05 +0530 |
| commit | 311d0244d6093ebdccee00d072016b7a7a1c9372 (patch) | |
| tree | 02f10e99abea8736d02fc46a12895bcad2743cf6 /library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.cir | |
| parent | ae99d42b8d2ffeaf91f96d5ffbe5efe91214cf0c (diff) | |
| parent | 053d7b4f66655f04b4965b26ffea0125cab1ccdd (diff) | |
| download | eSim-311d0244d6093ebdccee00d072016b7a7a1c9372.tar.gz eSim-311d0244d6093ebdccee00d072016b7a7a1c9372.tar.bz2 eSim-311d0244d6093ebdccee00d072016b7a7a1c9372.zip | |
Subcircuit files for different ICs
Diffstat (limited to 'library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.cir')
| -rw-r--r-- | library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.cir | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.cir b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.cir new file mode 100644 index 00000000..68e79d37 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.cir @@ -0,0 +1,21 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\NAND_GATE_FINAL\NAND_GATE_FINAL.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 01/12/25 21:38:44 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q2 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +R1 Net-_R1-Pad1_ Net-_Q1-Pad2_ 4k +R2 Net-_R1-Pad1_ Net-_Q3-Pad1_ 1.6k +R4 Net-_Q4-Pad1_ Net-_R1-Pad1_ 130 +Q4 Net-_Q4-Pad1_ Net-_Q3-Pad1_ Net-_D1-Pad1_ eSim_NPN +Q3 Net-_Q3-Pad1_ Net-_Q1-Pad1_ Net-_Q3-Pad3_ eSim_NPN +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +Q5 Net-_D1-Pad2_ Net-_Q3-Pad3_ GND eSim_NPN +R3 Net-_Q3-Pad3_ GND 1k +U1 Net-_Q1-Pad3_ Net-_Q2-Pad3_ Net-_D1-Pad2_ Net-_R1-Pad1_ PORT + +.end |