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| author | Sumanto Kar | 2024-11-19 11:46:50 +0530 |
|---|---|---|
| committer | GitHub | 2024-11-19 11:46:50 +0530 |
| commit | 84061eca7de0c15700012c8627aade77c60a05c7 (patch) | |
| tree | 2e4a5fbc1925b8abdc126a2d8a7ee45163acd8ad /library/SubcircuitLibrary/SN7483A_sub/4_OR.cir.out | |
| parent | 3989889835663988f3dc89f1c1b0a8c5e23e303d (diff) | |
| download | eSim-84061eca7de0c15700012c8627aade77c60a05c7.tar.gz eSim-84061eca7de0c15700012c8627aade77c60a05c7.tar.bz2 eSim-84061eca7de0c15700012c8627aade77c60a05c7.zip | |
Subcircuit Files of ICs(Contributor: Sudheshna Prabakaran) (#285)
* Removed distutils dependency
shutil can be used in place of distutils .
* Integrated Schematic Converters (#271)
Add the files for the Schematic Converters(PSpice to KiCad and LTspice to KiCad converters) to eSim.
* SN7445 is a BCD-To-Decimal Decoders/Drivers
* LM323A is a 3.0 A Positive Voltage Regulator
* LM341 is a 500-mA, 35-V, linear voltage regulator
* LM384 is a power audio amplifier
* CA3140 Series Operational Amplifiers
* LM111, LM211, and LM311 devices are single high-speed voltage comparators
* 74HC688 is an 8-bit magnitude comparator
* 7483:4-BIT BINARY FULL ADDDERS WITH FAST CARRY
* LM102 series are high-gain operational amplifiers
* The LM110 - An Improved IC Voltage Follower
* LM123/LM323A/LM323-N 3-Amp, 5-Volt Positive Regulator
* LM384 is a power audio amplifier
---------
Co-authored-by: Abinash Singh <162575828+avinashlalotra@users.noreply.github.com>
Co-authored-by: SangaviGR <125533330+SangaviGR@users.noreply.github.com>
Diffstat (limited to 'library/SubcircuitLibrary/SN7483A_sub/4_OR.cir.out')
| -rw-r--r-- | library/SubcircuitLibrary/SN7483A_sub/4_OR.cir.out | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/SN7483A_sub/4_OR.cir.out b/library/SubcircuitLibrary/SN7483A_sub/4_OR.cir.out new file mode 100644 index 00000000..adb6b01b --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/4_OR.cir.out @@ -0,0 +1,24 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end |