Merge pull request #303 from Rachith-H/master

Subcircuit Files for different IC's

1 files changed, 117 insertions, 0 deletions

diff --git a/library/SubcircuitLibrary/SN74351/SN74351.cir.out b/library/SubcircuitLibrary/SN74351/SN74351.cir.out
new file mode 100644
index 00000000..07b597bb
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74351/SN74351.cir.out
@@ -0,0 +1,117 @@
+* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\sn74351\sn74351.cir
+
+.include 5_and.sub
+x1 net-_u1-pad6_ net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u20-pad1_ net-_u6-pad1_ 5_and
+x2 net-_u1-pad7_ net-_u1-pad3_ net-_u3-pad2_ net-_u4-pad2_ net-_u20-pad1_ net-_u6-pad2_ 5_and
+x3 net-_u1-pad8_ net-_u2-pad2_ net-_u1-pad4_ net-_u4-pad2_ net-_u20-pad1_ net-_u7-pad1_ 5_and
+x4 net-_u1-pad9_ net-_u1-pad3_ net-_u1-pad4_ net-_u4-pad2_ net-_u20-pad1_ net-_u7-pad2_ 5_and
+x5 net-_u1-pad14_ net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad5_ net-_u20-pad1_ net-_u9-pad1_ 5_and
+x6 net-_u1-pad13_ net-_u1-pad3_ net-_u3-pad2_ net-_u1-pad5_ net-_u20-pad1_ net-_u9-pad2_ 5_and
+x7 net-_u1-pad12_ net-_u2-pad2_ net-_u1-pad4_ net-_u1-pad5_ net-_u20-pad1_ net-_u11-pad1_ 5_and
+x8 net-_u1-pad11_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u20-pad1_ net-_u11-pad2_ 5_and
+x9 net-_u20-pad1_ net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad11_ net-_u8-pad1_ 5_and
+x10 net-_u20-pad1_ net-_u1-pad5_ net-_u1-pad4_ net-_u2-pad2_ net-_u1-pad12_ net-_u8-pad2_ 5_and
+x11 net-_u20-pad1_ net-_u1-pad5_ net-_u3-pad2_ net-_u1-pad3_ net-_u1-pad13_ net-_u10-pad1_ 5_and
+x12 net-_u20-pad1_ net-_u1-pad5_ net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad14_ net-_u10-pad2_ 5_and
+x13 net-_u20-pad1_ net-_u4-pad2_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad15_ net-_u12-pad1_ 5_and
+x14 net-_u20-pad1_ net-_u2-pad2_ net-_u4-pad2_ net-_u1-pad4_ net-_u1-pad16_ net-_u12-pad2_ 5_and
+x15 net-_u20-pad1_ net-_u4-pad2_ net-_u3-pad2_ net-_u1-pad3_ net-_u1-pad17_ net-_u13-pad1_ 5_and
+x16 net-_u20-pad1_ net-_u4-pad2_ net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad18_ net-_u13-pad2_ 5_and
+* u5  net-_u1-pad2_ net-_u20-pad1_ d_inverter
+* u2  net-_u1-pad3_ net-_u2-pad2_ d_inverter
+* u3  net-_u1-pad4_ net-_u3-pad2_ d_inverter
+* u4  net-_u1-pad5_ net-_u4-pad2_ d_inverter
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ ? net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ ? port
+* u20  net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad1_ d_and
+* u21  net-_u20-pad1_ net-_u21-pad2_ net-_u1-pad19_ d_and
+* u18  net-_u14-pad3_ net-_u16-pad3_ net-_u18-pad3_ d_or
+* u14  net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_or
+* u16  net-_u16-pad1_ net-_u11-pad3_ net-_u16-pad3_ d_or
+* u11  net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_or
+* u9  net-_u9-pad1_ net-_u9-pad2_ net-_u16-pad1_ d_or
+* u7  net-_u7-pad1_ net-_u7-pad2_ net-_u14-pad2_ d_or
+* u6  net-_u6-pad1_ net-_u6-pad2_ net-_u14-pad1_ d_or
+* u19  net-_u15-pad3_ net-_u17-pad3_ net-_u19-pad3_ d_or
+* u17  net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_or
+* u15  net-_u15-pad1_ net-_u10-pad3_ net-_u15-pad3_ d_or
+* u8  net-_u8-pad1_ net-_u8-pad2_ net-_u15-pad1_ d_or
+* u10  net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_or
+* u12  net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_or
+* u13  net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_or
+* u22  net-_u18-pad3_ net-_u20-pad2_ d_inverter
+* u23  net-_u19-pad3_ net-_u21-pad2_ d_inverter
+a1 net-_u1-pad2_ net-_u20-pad1_ u5
+a2 net-_u1-pad3_ net-_u2-pad2_ u2
+a3 net-_u1-pad4_ net-_u3-pad2_ u3
+a4 net-_u1-pad5_ net-_u4-pad2_ u4
+a5 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad1_ u20
+a6 [net-_u20-pad1_ net-_u21-pad2_ ] net-_u1-pad19_ u21
+a7 [net-_u14-pad3_ net-_u16-pad3_ ] net-_u18-pad3_ u18
+a8 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14
+a9 [net-_u16-pad1_ net-_u11-pad3_ ] net-_u16-pad3_ u16
+a10 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a11 [net-_u9-pad1_ net-_u9-pad2_ ] net-_u16-pad1_ u9
+a12 [net-_u7-pad1_ net-_u7-pad2_ ] net-_u14-pad2_ u7
+a13 [net-_u6-pad1_ net-_u6-pad2_ ] net-_u14-pad1_ u6
+a14 [net-_u15-pad3_ net-_u17-pad3_ ] net-_u19-pad3_ u19
+a15 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17
+a16 [net-_u15-pad1_ net-_u10-pad3_ ] net-_u15-pad3_ u15
+a17 [net-_u8-pad1_ net-_u8-pad2_ ] net-_u15-pad1_ u8
+a18 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a19 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+a20 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13
+a21 net-_u18-pad3_ net-_u20-pad2_ u22
+a22 net-_u19-pad3_ net-_u21-pad2_ u23
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u18 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u14 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u16 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u11 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u9 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u7 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u19 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u17 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u15 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u8 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u10 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u12 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u13 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u22 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u23 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end