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| author | Sumanto Kar | 2025-02-23 17:20:17 +0530 |
|---|---|---|
| committer | GitHub | 2025-02-23 17:20:17 +0530 |
| commit | ae99d42b8d2ffeaf91f96d5ffbe5efe91214cf0c (patch) | |
| tree | e28be9a5dd152dd76d593ea9541d95305bbb059b /library/SubcircuitLibrary/SN74351/5_and.cir.out | |
| parent | 679e6ad8242e09d69576208c9fffaa3694a41b70 (diff) | |
| parent | b712ae83d0802e76c2760e49cc6c03b5eaa190dc (diff) | |
| download | eSim-ae99d42b8d2ffeaf91f96d5ffbe5efe91214cf0c.tar.gz eSim-ae99d42b8d2ffeaf91f96d5ffbe5efe91214cf0c.tar.bz2 eSim-ae99d42b8d2ffeaf91f96d5ffbe5efe91214cf0c.zip | |
Merge pull request #303 from Rachith-H/master
Subcircuit Files for different IC's
Diffstat (limited to 'library/SubcircuitLibrary/SN74351/5_and.cir.out')
| -rw-r--r-- | library/SubcircuitLibrary/SN74351/5_and.cir.out | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/SN74351/5_and.cir.out b/library/SubcircuitLibrary/SN74351/5_and.cir.out new file mode 100644 index 00000000..6a6b126a --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/5_and.cir.out @@ -0,0 +1,22 @@ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end |