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| author | Aditya Minocha | 2024-08-25 21:34:06 +0530 |
|---|---|---|
| committer | GitHub | 2024-08-25 21:34:06 +0530 |
| commit | 7f60ce39c1e72fff19153772e66a628f9678e5c9 (patch) | |
| tree | 34df2c39041c02ff50dc5fbc0aecf1d1298305a5 /library/SubcircuitLibrary/SN54HC148/3_and.cir.out | |
| parent | 4148cefab1bccb6c2cd4ae3606e5450cf090dac0 (diff) | |
| download | eSim-7f60ce39c1e72fff19153772e66a628f9678e5c9.tar.gz eSim-7f60ce39c1e72fff19153772e66a628f9678e5c9.tar.bz2 eSim-7f60ce39c1e72fff19153772e66a628f9678e5c9.zip | |
SN54HC148 IC - 8:3 Priority Encoder
Diffstat (limited to 'library/SubcircuitLibrary/SN54HC148/3_and.cir.out')
| -rw-r--r-- | library/SubcircuitLibrary/SN54HC148/3_and.cir.out | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/SN54HC148/3_and.cir.out b/library/SubcircuitLibrary/SN54HC148/3_and.cir.out new file mode 100644 index 00000000..e3c96645 --- /dev/null +++ b/library/SubcircuitLibrary/SN54HC148/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
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