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| author | Sumanto Kar | 2025-07-09 00:20:46 +0530 |
|---|---|---|
| committer | GitHub | 2025-07-09 00:20:46 +0530 |
| commit | bde08bd0437ddde78af8c35bf8bbb3a142dae1c3 (patch) | |
| tree | e63c40c489305f1f5c9f5f44702ab34a31a8bebf /library/SubcircuitLibrary/SN54F71/sn54f71.cir.out | |
| parent | 2b505cec4b63dd9744f0a68536b0df305de0022c (diff) | |
| parent | 42ff75fcbf7bc0ec42b054d0f7850b4ddddb3d63 (diff) | |
| download | eSim-master.tar.gz eSim-master.tar.bz2 eSim-master.zip | |
Adding Subcircuits for Analog and Digital IC's in eSim
Diffstat (limited to 'library/SubcircuitLibrary/SN54F71/sn54f71.cir.out')
| -rw-r--r-- | library/SubcircuitLibrary/SN54F71/sn54f71.cir.out | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/SN54F71/sn54f71.cir.out b/library/SubcircuitLibrary/SN54F71/sn54f71.cir.out new file mode 100644 index 00000000..f49eeb3a --- /dev/null +++ b/library/SubcircuitLibrary/SN54F71/sn54f71.cir.out @@ -0,0 +1,31 @@ +* d:\fossee\msys\dev\fossee\esim\library\subcircuitlibrary\sn54f71\sn54f71.cir
+
+.include 3_and.sub
+* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_and
+* u3 net-_u1-pad4_ net-_u1-pad5_ net-_u3-pad3_ d_and
+x2 net-_u1-pad1_ net-_u1-pad12_ net-_u1-pad13_ net-_u4-pad1_ 3_and
+x1 net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u4-pad2_ 3_and
+* u5 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad6_ d_nor
+* u4 net-_u4-pad1_ net-_u4-pad2_ net-_u1-pad8_ d_nor
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
+a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad6_ u5
+a4 [net-_u4-pad1_ net-_u4-pad2_ ] net-_u1-pad8_ u4
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u4 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
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