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| author | Aditya Minocha | 2024-08-25 21:58:26 +0530 |
|---|---|---|
| committer | GitHub | 2024-08-25 21:58:26 +0530 |
| commit | 7b98810d458d8cf7a68ff62831ab8ea1cc5846f8 (patch) | |
| tree | 68cabb9841a619ecc0280dde27f0be7b3ba39d0f /library/SubcircuitLibrary/Logic_Gates/XOR.sub | |
| parent | e8f999d879320df46aaec04605cb92ff06ad4809 (diff) | |
| download | eSim-7b98810d458d8cf7a68ff62831ab8ea1cc5846f8.tar.gz eSim-7b98810d458d8cf7a68ff62831ab8ea1cc5846f8.tar.bz2 eSim-7b98810d458d8cf7a68ff62831ab8ea1cc5846f8.zip | |
Logic Gates
Diffstat (limited to 'library/SubcircuitLibrary/Logic_Gates/XOR.sub')
| -rw-r--r-- | library/SubcircuitLibrary/Logic_Gates/XOR.sub | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/Logic_Gates/XOR.sub b/library/SubcircuitLibrary/Logic_Gates/XOR.sub new file mode 100644 index 00000000..b3260e83 --- /dev/null +++ b/library/SubcircuitLibrary/Logic_Gates/XOR.sub @@ -0,0 +1,20 @@ +* Subcircuit XOR
+.subckt XOR net-_m1-pad2_ net-_m2-pad2_ net-_m1-pad1_
+* c:\fossee\esim\library\subcircuitlibrary\xor\xor.cir
+.include NOT.sub
+.include NMOS-180nm.lib
+.include PMOS-180nm.lib
+m2 net-_m1-pad3_ net-_m2-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m8 net-_m7-pad3_ net-_m6-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m7 net-_m1-pad1_ net-_m4-pad2_ net-_m7-pad3_ net-_m7-pad3_ CMOSN W=100u L=100u M=1
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m4 net-_m3-pad3_ net-_m4-pad2_ net-_m1-pad1_ net-_m3-pad3_ CMOSP W=100u L=100u M=1
+m6 net-_m3-pad3_ net-_m6-pad2_ net-_m1-pad1_ net-_m3-pad3_ CMOSP W=100u L=100u M=1
+m3 net-_m3-pad1_ net-_m1-pad2_ net-_m3-pad3_ net-_m3-pad1_ CMOSP W=100u L=100u M=1
+m5 net-_m3-pad1_ net-_m2-pad2_ net-_m3-pad3_ net-_m3-pad1_ CMOSP W=100u L=100u M=1
+x1 net-_m1-pad2_ net-_m4-pad2_ NOT
+x2 net-_m2-pad2_ net-_m6-pad2_ NOT
+v1 net-_m3-pad1_ gnd dc 1.8
+* Control Statements
+
+.ends XOR
\ No newline at end of file |