Merge pull request #303 from Rachith-H/master

Subcircuit Files for different IC's

8 files changed, 1440 insertions, 0 deletions

diff --git a/library/SubcircuitLibrary/HD74LS152/HD74LS152-cache.lib b/library/SubcircuitLibrary/HD74LS152/HD74LS152-cache.lib
new file mode 100644
index 00000000..889b4267
--- /dev/null
+++ b/library/SubcircuitLibrary/HD74LS152/HD74LS152-cache.lib
@@ -0,0 +1,94 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/HD74LS152/HD74LS152.cir b/library/SubcircuitLibrary/HD74LS152/HD74LS152.cir
new file mode 100644
index 00000000..e0c1478f
--- /dev/null
+++ b/library/SubcircuitLibrary/HD74LS152/HD74LS152.cir
@@ -0,0 +1,49 @@
+* C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\HD74LS152\HD74LS152.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 01/18/25 21:34:43
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U8  Net-_U1-Pad5_ Net-_U12-Pad2_ Net-_U24-Pad1_ d_and		
+U9  Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U24-Pad2_ d_and		
+U10  Net-_U1-Pad4_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and		
+U11  Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and		
+U12  Net-_U1-Pad3_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_and		
+U13  Net-_U13-Pad1_ Net-_U11-Pad2_ Net-_U13-Pad3_ d_and		
+U14  Net-_U1-Pad2_ Net-_U10-Pad2_ Net-_U14-Pad3_ d_and		
+U15  Net-_U13-Pad1_ Net-_U11-Pad2_ Net-_U15-Pad3_ d_and		
+U16  Net-_U1-Pad1_ Net-_U12-Pad2_ Net-_U16-Pad3_ d_and		
+U17  Net-_U11-Pad1_ Net-_U17-Pad2_ Net-_U17-Pad3_ d_and		
+U18  Net-_U1-Pad13_ Net-_U10-Pad2_ Net-_U18-Pad3_ d_and		
+U19  Net-_U11-Pad1_ Net-_U17-Pad2_ Net-_U19-Pad3_ d_and		
+U20  Net-_U1-Pad12_ Net-_U12-Pad2_ Net-_U20-Pad3_ d_and		
+U21  Net-_U13-Pad1_ Net-_U17-Pad2_ Net-_U21-Pad3_ d_and		
+U22  Net-_U1-Pad11_ Net-_U10-Pad2_ Net-_U22-Pad3_ d_and		
+U23  Net-_U13-Pad1_ Net-_U17-Pad2_ Net-_U23-Pad3_ d_and		
+U32  Net-_U24-Pad3_ Net-_U25-Pad3_ Net-_U32-Pad3_ d_or		
+U24  Net-_U24-Pad1_ Net-_U24-Pad2_ Net-_U24-Pad3_ d_and		
+U25  Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U25-Pad3_ d_and		
+U26  Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U26-Pad3_ d_and		
+U27  Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U27-Pad3_ d_and		
+U28  Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U28-Pad3_ d_and		
+U29  Net-_U18-Pad3_ Net-_U19-Pad3_ Net-_U29-Pad3_ d_and		
+U30  Net-_U20-Pad3_ Net-_U21-Pad3_ Net-_U30-Pad3_ d_and		
+U31  Net-_U22-Pad3_ Net-_U23-Pad3_ Net-_U31-Pad3_ d_and		
+U33  Net-_U26-Pad3_ Net-_U27-Pad3_ Net-_U33-Pad3_ d_or		
+U35  Net-_U28-Pad3_ Net-_U29-Pad3_ Net-_U35-Pad3_ d_or		
+U34  Net-_U30-Pad3_ Net-_U31-Pad3_ Net-_U34-Pad3_ d_or		
+U36  Net-_U32-Pad3_ Net-_U33-Pad3_ Net-_U36-Pad3_ d_or		
+U37  Net-_U35-Pad3_ Net-_U34-Pad3_ Net-_U37-Pad3_ d_or		
+U38  Net-_U36-Pad3_ Net-_U37-Pad3_ Net-_U38-Pad3_ d_or		
+U39  Net-_U38-Pad3_ Net-_U1-Pad6_ d_inverter		
+U4  Net-_U1-Pad10_ Net-_U12-Pad2_ d_inverter		
+U7  Net-_U12-Pad2_ Net-_U10-Pad2_ d_inverter		
+U2  Net-_U1-Pad9_ Net-_U11-Pad1_ d_inverter		
+U5  Net-_U11-Pad1_ Net-_U13-Pad1_ d_inverter		
+U3  Net-_U1-Pad8_ Net-_U11-Pad2_ d_inverter		
+U6  Net-_U11-Pad2_ Net-_U17-Pad2_ d_inverter		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/HD74LS152/HD74LS152.cir.out b/library/SubcircuitLibrary/HD74LS152/HD74LS152.cir.out
new file mode 100644
index 00000000..db09e46d
--- /dev/null
+++ b/library/SubcircuitLibrary/HD74LS152/HD74LS152.cir.out
@@ -0,0 +1,164 @@
+* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\hd74ls152\hd74ls152.cir
+
+* u8  net-_u1-pad5_ net-_u12-pad2_ net-_u24-pad1_ d_and
+* u9  net-_u11-pad1_ net-_u11-pad2_ net-_u24-pad2_ d_and
+* u10  net-_u1-pad4_ net-_u10-pad2_ net-_u10-pad3_ d_and
+* u11  net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and
+* u12  net-_u1-pad3_ net-_u12-pad2_ net-_u12-pad3_ d_and
+* u13  net-_u13-pad1_ net-_u11-pad2_ net-_u13-pad3_ d_and
+* u14  net-_u1-pad2_ net-_u10-pad2_ net-_u14-pad3_ d_and
+* u15  net-_u13-pad1_ net-_u11-pad2_ net-_u15-pad3_ d_and
+* u16  net-_u1-pad1_ net-_u12-pad2_ net-_u16-pad3_ d_and
+* u17  net-_u11-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_and
+* u18  net-_u1-pad13_ net-_u10-pad2_ net-_u18-pad3_ d_and
+* u19  net-_u11-pad1_ net-_u17-pad2_ net-_u19-pad3_ d_and
+* u20  net-_u1-pad12_ net-_u12-pad2_ net-_u20-pad3_ d_and
+* u21  net-_u13-pad1_ net-_u17-pad2_ net-_u21-pad3_ d_and
+* u22  net-_u1-pad11_ net-_u10-pad2_ net-_u22-pad3_ d_and
+* u23  net-_u13-pad1_ net-_u17-pad2_ net-_u23-pad3_ d_and
+* u32  net-_u24-pad3_ net-_u25-pad3_ net-_u32-pad3_ d_or
+* u24  net-_u24-pad1_ net-_u24-pad2_ net-_u24-pad3_ d_and
+* u25  net-_u10-pad3_ net-_u11-pad3_ net-_u25-pad3_ d_and
+* u26  net-_u12-pad3_ net-_u13-pad3_ net-_u26-pad3_ d_and
+* u27  net-_u14-pad3_ net-_u15-pad3_ net-_u27-pad3_ d_and
+* u28  net-_u16-pad3_ net-_u17-pad3_ net-_u28-pad3_ d_and
+* u29  net-_u18-pad3_ net-_u19-pad3_ net-_u29-pad3_ d_and
+* u30  net-_u20-pad3_ net-_u21-pad3_ net-_u30-pad3_ d_and
+* u31  net-_u22-pad3_ net-_u23-pad3_ net-_u31-pad3_ d_and
+* u33  net-_u26-pad3_ net-_u27-pad3_ net-_u33-pad3_ d_or
+* u35  net-_u28-pad3_ net-_u29-pad3_ net-_u35-pad3_ d_or
+* u34  net-_u30-pad3_ net-_u31-pad3_ net-_u34-pad3_ d_or
+* u36  net-_u32-pad3_ net-_u33-pad3_ net-_u36-pad3_ d_or
+* u37  net-_u35-pad3_ net-_u34-pad3_ net-_u37-pad3_ d_or
+* u38  net-_u36-pad3_ net-_u37-pad3_ net-_u38-pad3_ d_or
+* u39  net-_u38-pad3_ net-_u1-pad6_ d_inverter
+* u4  net-_u1-pad10_ net-_u12-pad2_ d_inverter
+* u7  net-_u12-pad2_ net-_u10-pad2_ d_inverter
+* u2  net-_u1-pad9_ net-_u11-pad1_ d_inverter
+* u5  net-_u11-pad1_ net-_u13-pad1_ d_inverter
+* u3  net-_u1-pad8_ net-_u11-pad2_ d_inverter
+* u6  net-_u11-pad2_ net-_u17-pad2_ d_inverter
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
+a1 [net-_u1-pad5_ net-_u12-pad2_ ] net-_u24-pad1_ u8
+a2 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u24-pad2_ u9
+a3 [net-_u1-pad4_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a4 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a5 [net-_u1-pad3_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+a6 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u13-pad3_ u13
+a7 [net-_u1-pad2_ net-_u10-pad2_ ] net-_u14-pad3_ u14
+a8 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u15-pad3_ u15
+a9 [net-_u1-pad1_ net-_u12-pad2_ ] net-_u16-pad3_ u16
+a10 [net-_u11-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17
+a11 [net-_u1-pad13_ net-_u10-pad2_ ] net-_u18-pad3_ u18
+a12 [net-_u11-pad1_ net-_u17-pad2_ ] net-_u19-pad3_ u19
+a13 [net-_u1-pad12_ net-_u12-pad2_ ] net-_u20-pad3_ u20
+a14 [net-_u13-pad1_ net-_u17-pad2_ ] net-_u21-pad3_ u21
+a15 [net-_u1-pad11_ net-_u10-pad2_ ] net-_u22-pad3_ u22
+a16 [net-_u13-pad1_ net-_u17-pad2_ ] net-_u23-pad3_ u23
+a17 [net-_u24-pad3_ net-_u25-pad3_ ] net-_u32-pad3_ u32
+a18 [net-_u24-pad1_ net-_u24-pad2_ ] net-_u24-pad3_ u24
+a19 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u25-pad3_ u25
+a20 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u26-pad3_ u26
+a21 [net-_u14-pad3_ net-_u15-pad3_ ] net-_u27-pad3_ u27
+a22 [net-_u16-pad3_ net-_u17-pad3_ ] net-_u28-pad3_ u28
+a23 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u29-pad3_ u29
+a24 [net-_u20-pad3_ net-_u21-pad3_ ] net-_u30-pad3_ u30
+a25 [net-_u22-pad3_ net-_u23-pad3_ ] net-_u31-pad3_ u31
+a26 [net-_u26-pad3_ net-_u27-pad3_ ] net-_u33-pad3_ u33
+a27 [net-_u28-pad3_ net-_u29-pad3_ ] net-_u35-pad3_ u35
+a28 [net-_u30-pad3_ net-_u31-pad3_ ] net-_u34-pad3_ u34
+a29 [net-_u32-pad3_ net-_u33-pad3_ ] net-_u36-pad3_ u36
+a30 [net-_u35-pad3_ net-_u34-pad3_ ] net-_u37-pad3_ u37
+a31 [net-_u36-pad3_ net-_u37-pad3_ ] net-_u38-pad3_ u38
+a32 net-_u38-pad3_ net-_u1-pad6_ u39
+a33 net-_u1-pad10_ net-_u12-pad2_ u4
+a34 net-_u12-pad2_ net-_u10-pad2_ u7
+a35 net-_u1-pad9_ net-_u11-pad1_ u2
+a36 net-_u11-pad1_ net-_u13-pad1_ u5
+a37 net-_u1-pad8_ net-_u11-pad2_ u3
+a38 net-_u11-pad2_ net-_u17-pad2_ u6
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u32 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u33 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u35 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u34 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u36 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u37 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u38 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u39 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/HD74LS152/HD74LS152.pro b/library/SubcircuitLibrary/HD74LS152/HD74LS152.pro
new file mode 100644
index 00000000..f63b751e
--- /dev/null
+++ b/library/SubcircuitLibrary/HD74LS152/HD74LS152.pro
@@ -0,0 +1,69 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
diff --git a/library/SubcircuitLibrary/HD74LS152/HD74LS152.sch b/library/SubcircuitLibrary/HD74LS152/HD74LS152.sch
new file mode 100644
index 00000000..70c27f62
--- /dev/null
+++ b/library/SubcircuitLibrary/HD74LS152/HD74LS152.sch
@@ -0,0 +1,904 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:HD74LS152-cache
+EELAYER 25 0
+EELAYER END
+$Descr A2 23386 16535
+encoding utf-8
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+	6600 9350 11350 9350
+Wire Wire Line
+	11350 8600 6750 8600
+Wire Wire Line
+	11350 7900 6700 7900
+Wire Wire Line
+	11350 7200 6700 7200
+Wire Wire Line
+	11350 6500 6700 6500
+Wire Wire Line
+	11350 5750 6700 5750
+Wire Wire Line
+	11350 5050 6750 5050
+Wire Wire Line
+	13300 6700 14200 6700
+Wire Wire Line
+	14200 6700 14200 7000
+Wire Wire Line
+	14200 7000 14400 7000
+Wire Wire Line
+	14400 7100 14200 7100
+Wire Wire Line
+	14200 7100 14200 7400
+Wire Wire Line
+	14200 7400 13300 7400
+Wire Wire Line
+	13300 8150 14200 8150
+Wire Wire Line
+	14200 8150 14200 8350
+Wire Wire Line
+	14200 8350 14450 8350
+Wire Wire Line
+	14450 8450 14200 8450
+Wire Wire Line
+	14200 8450 14200 8800
+Wire Wire Line
+	14200 8800 13300 8800
+Wire Wire Line
+	13300 9500 14050 9500
+Wire Wire Line
+	14050 9500 14050 9650
+Wire Wire Line
+	14050 9650 14400 9650
+Wire Wire Line
+	14400 9750 14050 9750
+Wire Wire Line
+	14050 9750 14050 10250
+Wire Wire Line
+	14050 10250 13300 10250
+Wire Wire Line
+	13300 5250 13700 5250
+Wire Wire Line
+	13700 5250 13700 5600
+Wire Wire Line
+	13700 5600 14350 5600
+Wire Wire Line
+	14350 5700 13700 5700
+Wire Wire Line
+	13700 5700 13700 5950
+Wire Wire Line
+	13700 5950 13300 5950
+Wire Wire Line
+	15250 5650 15450 5650
+Wire Wire Line
+	15450 5650 15450 6550
+Wire Wire Line
+	15450 6550 15700 6550
+Wire Wire Line
+	15700 6650 15500 6650
+Wire Wire Line
+	15500 6650 15500 7050
+Wire Wire Line
+	15500 7050 15300 7050
+Wire Wire Line
+	15350 8400 15550 8400
+Wire Wire Line
+	15550 8400 15550 9100
+Wire Wire Line
+	15550 9100 15750 9100
+Wire Wire Line
+	15750 9200 15550 9200
+Wire Wire Line
+	15550 9200 15550 9700
+Wire Wire Line
+	15550 9700 15300 9700
+Wire Wire Line
+	16600 6600 16800 6600
+Wire Wire Line
+	16800 6600 16800 7750
+Wire Wire Line
+	16800 7750 16900 7750
+Wire Wire Line
+	16900 7850 16800 7850
+Wire Wire Line
+	16800 7850 16800 9150
+Wire Wire Line
+	16800 9150 16650 9150
+Wire Wire Line
+	17800 7800 18000 7800
+Wire Wire Line
+	18600 7800 18950 7800
+Wire Wire Line
+	6450 11250 6100 11250
+Wire Wire Line
+	6400 11950 6100 11950
+Wire Wire Line
+	6400 12700 6100 12700
+$Comp
+L PORT U1
+U 6 1 678BA160
+P 19200 7800
+F 0 "U1" H 19250 7900 30  0000 C CNN
+F 1 "PORT" H 19200 7800 30  0000 C CNN
+F 2 "" H 19200 7800 60  0000 C CNN
+F 3 "" H 19200 7800 60  0000 C CNN
+	6    19200 7800
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 5 1 678BA3D2
+P 6500 5050
+F 0 "U1" H 6550 5150 30  0000 C CNN
+F 1 "PORT" H 6500 5050 30  0000 C CNN
+F 2 "" H 6500 5050 60  0000 C CNN
+F 3 "" H 6500 5050 60  0000 C CNN
+	5    6500 5050
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 678BA4DF
+P 6450 5750
+F 0 "U1" H 6500 5850 30  0000 C CNN
+F 1 "PORT" H 6450 5750 30  0000 C CNN
+F 2 "" H 6450 5750 60  0000 C CNN
+F 3 "" H 6450 5750 60  0000 C CNN
+	4    6450 5750
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 678BA54C
+P 6450 6500
+F 0 "U1" H 6500 6600 30  0000 C CNN
+F 1 "PORT" H 6450 6500 30  0000 C CNN
+F 2 "" H 6450 6500 60  0000 C CNN
+F 3 "" H 6450 6500 60  0000 C CNN
+	3    6450 6500
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 678BA63F
+P 6450 7200
+F 0 "U1" H 6500 7300 30  0000 C CNN
+F 1 "PORT" H 6450 7200 30  0000 C CNN
+F 2 "" H 6450 7200 60  0000 C CNN
+F 3 "" H 6450 7200 60  0000 C CNN
+	2    6450 7200
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 678BA760
+P 6450 7900
+F 0 "U1" H 6500 8000 30  0000 C CNN
+F 1 "PORT" H 6450 7900 30  0000 C CNN
+F 2 "" H 6450 7900 60  0000 C CNN
+F 3 "" H 6450 7900 60  0000 C CNN
+	1    6450 7900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 13 1 678BAA39
+P 6500 8600
+F 0 "U1" H 6550 8700 30  0000 C CNN
+F 1 "PORT" H 6500 8600 30  0000 C CNN
+F 2 "" H 6500 8600 60  0000 C CNN
+F 3 "" H 6500 8600 60  0000 C CNN
+	13   6500 8600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 12 1 678BAAB4
+P 6350 9350
+F 0 "U1" H 6400 9450 30  0000 C CNN
+F 1 "PORT" H 6350 9350 30  0000 C CNN
+F 2 "" H 6350 9350 60  0000 C CNN
+F 3 "" H 6350 9350 60  0000 C CNN
+	12   6350 9350
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 11 1 678BAB2F
+P 6350 10050
+F 0 "U1" H 6400 10150 30  0000 C CNN
+F 1 "PORT" H 6350 10050 30  0000 C CNN
+F 2 "" H 6350 10050 60  0000 C CNN
+F 3 "" H 6350 10050 60  0000 C CNN
+	11   6350 10050
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 10 1 678BAD20
+P 5850 11250
+F 0 "U1" H 5900 11350 30  0000 C CNN
+F 1 "PORT" H 5850 11250 30  0000 C CNN
+F 2 "" H 5850 11250 60  0000 C CNN
+F 3 "" H 5850 11250 60  0000 C CNN
+	10   5850 11250
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 9 1 678BAD9B
+P 5850 11950
+F 0 "U1" H 5900 12050 30  0000 C CNN
+F 1 "PORT" H 5850 11950 30  0000 C CNN
+F 2 "" H 5850 11950 60  0000 C CNN
+F 3 "" H 5850 11950 60  0000 C CNN
+	9    5850 11950
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 8 1 678BB0C4
+P 5850 12700
+F 0 "U1" H 5900 12800 30  0000 C CNN
+F 1 "PORT" H 5850 12700 30  0000 C CNN
+F 2 "" H 5850 12700 60  0000 C CNN
+F 3 "" H 5850 12700 60  0000 C CNN
+	8    5850 12700
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 7 1 678BB437
+P 13400 11500
+F 0 "U1" H 13450 11600 30  0000 C CNN
+F 1 "PORT" H 13400 11500 30  0000 C CNN
+F 2 "" H 13400 11500 60  0000 C CNN
+F 3 "" H 13400 11500 60  0000 C CNN
+	7    13400 11500
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 14 1 678BB54B
+P 13400 11750
+F 0 "U1" H 13450 11850 30  0000 C CNN
+F 1 "PORT" H 13400 11750 30  0000 C CNN
+F 2 "" H 13400 11750 60  0000 C CNN
+F 3 "" H 13400 11750 60  0000 C CNN
+	14   13400 11750
+	1    0    0    -1  
+$EndComp
+NoConn ~ 13650 11500
+NoConn ~ 13650 11750
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/HD74LS152/HD74LS152.sub b/library/SubcircuitLibrary/HD74LS152/HD74LS152.sub
new file mode 100644
index 00000000..3604a713
--- /dev/null
+++ b/library/SubcircuitLibrary/HD74LS152/HD74LS152.sub
@@ -0,0 +1,158 @@
+* Subcircuit HD74LS152
+.subckt HD74LS152 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? 
+* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\hd74ls152\hd74ls152.cir
+* u8  net-_u1-pad5_ net-_u12-pad2_ net-_u24-pad1_ d_and
+* u9  net-_u11-pad1_ net-_u11-pad2_ net-_u24-pad2_ d_and
+* u10  net-_u1-pad4_ net-_u10-pad2_ net-_u10-pad3_ d_and
+* u11  net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and
+* u12  net-_u1-pad3_ net-_u12-pad2_ net-_u12-pad3_ d_and
+* u13  net-_u13-pad1_ net-_u11-pad2_ net-_u13-pad3_ d_and
+* u14  net-_u1-pad2_ net-_u10-pad2_ net-_u14-pad3_ d_and
+* u15  net-_u13-pad1_ net-_u11-pad2_ net-_u15-pad3_ d_and
+* u16  net-_u1-pad1_ net-_u12-pad2_ net-_u16-pad3_ d_and
+* u17  net-_u11-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_and
+* u18  net-_u1-pad13_ net-_u10-pad2_ net-_u18-pad3_ d_and
+* u19  net-_u11-pad1_ net-_u17-pad2_ net-_u19-pad3_ d_and
+* u20  net-_u1-pad12_ net-_u12-pad2_ net-_u20-pad3_ d_and
+* u21  net-_u13-pad1_ net-_u17-pad2_ net-_u21-pad3_ d_and
+* u22  net-_u1-pad11_ net-_u10-pad2_ net-_u22-pad3_ d_and
+* u23  net-_u13-pad1_ net-_u17-pad2_ net-_u23-pad3_ d_and
+* u32  net-_u24-pad3_ net-_u25-pad3_ net-_u32-pad3_ d_or
+* u24  net-_u24-pad1_ net-_u24-pad2_ net-_u24-pad3_ d_and
+* u25  net-_u10-pad3_ net-_u11-pad3_ net-_u25-pad3_ d_and
+* u26  net-_u12-pad3_ net-_u13-pad3_ net-_u26-pad3_ d_and
+* u27  net-_u14-pad3_ net-_u15-pad3_ net-_u27-pad3_ d_and
+* u28  net-_u16-pad3_ net-_u17-pad3_ net-_u28-pad3_ d_and
+* u29  net-_u18-pad3_ net-_u19-pad3_ net-_u29-pad3_ d_and
+* u30  net-_u20-pad3_ net-_u21-pad3_ net-_u30-pad3_ d_and
+* u31  net-_u22-pad3_ net-_u23-pad3_ net-_u31-pad3_ d_and
+* u33  net-_u26-pad3_ net-_u27-pad3_ net-_u33-pad3_ d_or
+* u35  net-_u28-pad3_ net-_u29-pad3_ net-_u35-pad3_ d_or
+* u34  net-_u30-pad3_ net-_u31-pad3_ net-_u34-pad3_ d_or
+* u36  net-_u32-pad3_ net-_u33-pad3_ net-_u36-pad3_ d_or
+* u37  net-_u35-pad3_ net-_u34-pad3_ net-_u37-pad3_ d_or
+* u38  net-_u36-pad3_ net-_u37-pad3_ net-_u38-pad3_ d_or
+* u39  net-_u38-pad3_ net-_u1-pad6_ d_inverter
+* u4  net-_u1-pad10_ net-_u12-pad2_ d_inverter
+* u7  net-_u12-pad2_ net-_u10-pad2_ d_inverter
+* u2  net-_u1-pad9_ net-_u11-pad1_ d_inverter
+* u5  net-_u11-pad1_ net-_u13-pad1_ d_inverter
+* u3  net-_u1-pad8_ net-_u11-pad2_ d_inverter
+* u6  net-_u11-pad2_ net-_u17-pad2_ d_inverter
+a1 [net-_u1-pad5_ net-_u12-pad2_ ] net-_u24-pad1_ u8
+a2 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u24-pad2_ u9
+a3 [net-_u1-pad4_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a4 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a5 [net-_u1-pad3_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+a6 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u13-pad3_ u13
+a7 [net-_u1-pad2_ net-_u10-pad2_ ] net-_u14-pad3_ u14
+a8 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u15-pad3_ u15
+a9 [net-_u1-pad1_ net-_u12-pad2_ ] net-_u16-pad3_ u16
+a10 [net-_u11-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17
+a11 [net-_u1-pad13_ net-_u10-pad2_ ] net-_u18-pad3_ u18
+a12 [net-_u11-pad1_ net-_u17-pad2_ ] net-_u19-pad3_ u19
+a13 [net-_u1-pad12_ net-_u12-pad2_ ] net-_u20-pad3_ u20
+a14 [net-_u13-pad1_ net-_u17-pad2_ ] net-_u21-pad3_ u21
+a15 [net-_u1-pad11_ net-_u10-pad2_ ] net-_u22-pad3_ u22
+a16 [net-_u13-pad1_ net-_u17-pad2_ ] net-_u23-pad3_ u23
+a17 [net-_u24-pad3_ net-_u25-pad3_ ] net-_u32-pad3_ u32
+a18 [net-_u24-pad1_ net-_u24-pad2_ ] net-_u24-pad3_ u24
+a19 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u25-pad3_ u25
+a20 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u26-pad3_ u26
+a21 [net-_u14-pad3_ net-_u15-pad3_ ] net-_u27-pad3_ u27
+a22 [net-_u16-pad3_ net-_u17-pad3_ ] net-_u28-pad3_ u28
+a23 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u29-pad3_ u29
+a24 [net-_u20-pad3_ net-_u21-pad3_ ] net-_u30-pad3_ u30
+a25 [net-_u22-pad3_ net-_u23-pad3_ ] net-_u31-pad3_ u31
+a26 [net-_u26-pad3_ net-_u27-pad3_ ] net-_u33-pad3_ u33
+a27 [net-_u28-pad3_ net-_u29-pad3_ ] net-_u35-pad3_ u35
+a28 [net-_u30-pad3_ net-_u31-pad3_ ] net-_u34-pad3_ u34
+a29 [net-_u32-pad3_ net-_u33-pad3_ ] net-_u36-pad3_ u36
+a30 [net-_u35-pad3_ net-_u34-pad3_ ] net-_u37-pad3_ u37
+a31 [net-_u36-pad3_ net-_u37-pad3_ ] net-_u38-pad3_ u38
+a32 net-_u38-pad3_ net-_u1-pad6_ u39
+a33 net-_u1-pad10_ net-_u12-pad2_ u4
+a34 net-_u12-pad2_ net-_u10-pad2_ u7
+a35 net-_u1-pad9_ net-_u11-pad1_ u2
+a36 net-_u11-pad1_ net-_u13-pad1_ u5
+a37 net-_u1-pad8_ net-_u11-pad2_ u3
+a38 net-_u11-pad2_ net-_u17-pad2_ u6
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u32 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u33 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u35 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u34 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u36 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u37 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u38 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u39 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends HD74LS152
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/HD74LS152/HD74LS152_Previous_Values.xml b/library/SubcircuitLibrary/HD74LS152/HD74LS152_Previous_Values.xml
new file mode 100644
index 00000000..044e3a73
--- /dev/null
+++ b/library/SubcircuitLibrary/HD74LS152/HD74LS152_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u8 name="type">d_and<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Fall Delay (default=1.0e-9)" /></u8><u9 name="type">d_and<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Fall Delay (default=1.0e-9)" /></u9><u10 name="type">d_and<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Fall Delay (default=1.0e-9)" /></u10><u11 name="type">d_and<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /></u11><u12 name="type">d_and<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Fall Delay (default=1.0e-9)" /></u12><u13 name="type">d_and<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Fall Delay (default=1.0e-9)" /></u13><u14 name="type">d_and<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Fall Delay (default=1.0e-9)" /></u14><u15 name="type">d_and<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Fall Delay (default=1.0e-9)" /></u15><u16 name="type">d_and<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Fall Delay (default=1.0e-9)" /></u16><u17 name="type">d_and<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /></u17><u18 name="type">d_and<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Fall Delay (default=1.0e-9)" /></u18><u19 name="type">d_and<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Fall Delay (default=1.0e-9)" /></u19><u20 name="type">d_and<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Fall Delay (default=1.0e-9)" /></u20><u21 name="type">d_and<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Fall Delay (default=1.0e-9)" /></u21><u22 name="type">d_and<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Fall Delay (default=1.0e-9)" /></u22><u23 name="type">d_and<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Fall Delay (default=1.0e-9)" /></u23><u32 name="type">d_or<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Fall Delay (default=1.0e-9)" /></u32><u24 name="type">d_and<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Fall Delay (default=1.0e-9)" /></u24><u25 name="type">d_and<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Fall Delay (default=1.0e-9)" /></u25><u26 name="type">d_and<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Fall Delay (default=1.0e-9)" /></u26><u27 name="type">d_and<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Fall Delay (default=1.0e-9)" /></u27><u28 name="type">d_and<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Fall Delay (default=1.0e-9)" /></u28><u29 name="type">d_and<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Input Load (default=1.0e-12)" /><field69 name="Enter Fall Delay (default=1.0e-9)" /></u29><u30 name="type">d_and<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Input Load (default=1.0e-12)" /><field72 name="Enter Fall Delay (default=1.0e-9)" /></u30><u31 name="type">d_and<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Input Load (default=1.0e-12)" /><field75 name="Enter Fall Delay (default=1.0e-9)" /></u31><u33 name="type">d_or<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Input Load (default=1.0e-12)" /><field78 name="Enter Fall Delay (default=1.0e-9)" /></u33><u35 name="type">d_or<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Input Load (default=1.0e-12)" /><field81 name="Enter Fall Delay (default=1.0e-9)" /></u35><u34 name="type">d_or<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Input Load (default=1.0e-12)" /><field84 name="Enter Fall Delay (default=1.0e-9)" /></u34><u36 name="type">d_or<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Input Load (default=1.0e-12)" /><field87 name="Enter Fall Delay (default=1.0e-9)" /></u36><u37 name="type">d_or<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Input Load (default=1.0e-12)" /><field90 name="Enter Fall Delay (default=1.0e-9)" /></u37><u38 name="type">d_or<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Input Load (default=1.0e-12)" /><field93 name="Enter Fall Delay (default=1.0e-9)" /></u38><u39 name="type">d_inverter<field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Input Load (default=1.0e-12)" /><field96 name="Enter Fall Delay (default=1.0e-9)" /></u39><u4 name="type">d_inverter<field97 name="Enter Rise Delay (default=1.0e-9)" /><field98 name="Enter Input Load (default=1.0e-12)" /><field99 name="Enter Fall Delay (default=1.0e-9)" /></u4><u7 name="type">d_inverter<field100 name="Enter Rise Delay (default=1.0e-9)" /><field101 name="Enter Input Load (default=1.0e-12)" /><field102 name="Enter Fall Delay (default=1.0e-9)" /></u7><u2 name="type">d_inverter<field103 name="Enter Rise Delay (default=1.0e-9)" /><field104 name="Enter Input Load (default=1.0e-12)" /><field105 name="Enter Fall Delay (default=1.0e-9)" /></u2><u5 name="type">d_inverter<field106 name="Enter Rise Delay (default=1.0e-9)" /><field107 name="Enter Input Load (default=1.0e-12)" /><field108 name="Enter Fall Delay (default=1.0e-9)" /></u5><u3 name="type">d_inverter<field109 name="Enter Rise Delay (default=1.0e-9)" /><field110 name="Enter Input Load (default=1.0e-12)" /><field111 name="Enter Fall Delay (default=1.0e-9)" /></u3><u6 name="type">d_inverter<field112 name="Enter Rise Delay (default=1.0e-9)" /><field113 name="Enter Input Load (default=1.0e-12)" /><field114 name="Enter Fall Delay (default=1.0e-9)" /></u6></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/HD74LS152/analysis b/library/SubcircuitLibrary/HD74LS152/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/HD74LS152/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file