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authorAditya Minocha2024-08-25 21:57:05 +0530
committerGitHub2024-08-25 21:57:05 +0530
commite8f999d879320df46aaec04605cb92ff06ad4809 (patch)
tree8302564ddbd31c0b63eda373db82c6de34c1b5de /library/SubcircuitLibrary/Flip_Flops/NOT.cir
parent64a830500ffbadd67c42d008e68c52dfdc6f28d2 (diff)
downloadeSim-e8f999d879320df46aaec04605cb92ff06ad4809.tar.gz
eSim-e8f999d879320df46aaec04605cb92ff06ad4809.tar.bz2
eSim-e8f999d879320df46aaec04605cb92ff06ad4809.zip
Flip Flops
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diff --git a/library/SubcircuitLibrary/Flip_Flops/NOT.cir b/library/SubcircuitLibrary/Flip_Flops/NOT.cir
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+* C:\FOSSEE\eSim\library\SubcircuitLibrary\NOT\NOT.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/28/24 22:41:58
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ mosfet_n
+M2 Net-_M2-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad1_ Net-_M2-Pad1_ mosfet_p
+U1 Net-_M1-Pad2_ Net-_M1-Pad1_ Net-_M2-Pad1_ Net-_M1-Pad3_ PORT
+
+.end