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| author | Sumanto Kar | 2024-09-13 00:56:30 +0530 |
|---|---|---|
| committer | GitHub | 2024-09-13 00:56:30 +0530 |
| commit | 681978c7ce1aedee54b0ce6601b789edca226395 (patch) | |
| tree | fc4b37265699872bd87d9119e5334e9812a86f16 /library/SubcircuitLibrary/Flip_Flops/Flip_Flops.cir | |
| parent | 5f80292f451abd9c96849a277ec46670cd1446bc (diff) | |
| parent | 044059f99adcc13c41252126c12cc6f7bbed6b5f (diff) | |
| download | eSim-681978c7ce1aedee54b0ce6601b789edca226395.tar.gz eSim-681978c7ce1aedee54b0ce6601b789edca226395.tar.bz2 eSim-681978c7ce1aedee54b0ce6601b789edca226395.zip | |
Merge pull request #279 from AdityaMino/Aditya-Minocha
Subcircuit Files of ICs(Contributor: Aditya Minocha)
Diffstat (limited to 'library/SubcircuitLibrary/Flip_Flops/Flip_Flops.cir')
| -rw-r--r-- | library/SubcircuitLibrary/Flip_Flops/Flip_Flops.cir | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/Flip_Flops/Flip_Flops.cir b/library/SubcircuitLibrary/Flip_Flops/Flip_Flops.cir new file mode 100644 index 00000000..cf19e83a --- /dev/null +++ b/library/SubcircuitLibrary/Flip_Flops/Flip_Flops.cir @@ -0,0 +1,18 @@ +* C:\Users\Aditya\eSim-Workspace\Flip_Flops\Flip_Flops.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/03/24 12:03:16
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+v1 D GND pulse
+v2 clk GND pulse
+v3 PRE GND DC
+v4 CLR GND DC
+R1 Q GND 1000k
+R2 Qb GND 1000k
+v5 VCC GND DC
+X1 clk PRE D CLR GND VCC Q Qb D_Flip_Flop
+
+.end
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