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| author | Sumanto Kar | 2025-05-20 23:03:50 +0530 |
|---|---|---|
| committer | GitHub | 2025-05-20 23:03:50 +0530 |
| commit | ae8c87d0c73d0609bcaa89b25ef6fc1c1859cda5 (patch) | |
| tree | 7b914c3275132e27b4a57ea5f76e238ef15e29bd /library/SubcircuitLibrary/CY74FCT480T/74480.cir | |
| parent | 59551f0b573d803dbcd1f3008516447537caa85f (diff) | |
| parent | 5dd70b0967de8aba54962f6eb9a212b054b019b4 (diff) | |
| download | eSim-ae8c87d0c73d0609bcaa89b25ef6fc1c1859cda5.tar.gz eSim-ae8c87d0c73d0609bcaa89b25ef6fc1c1859cda5.tar.bz2 eSim-ae8c87d0c73d0609bcaa89b25ef6fc1c1859cda5.zip | |
Merge pull request #337 from Tanisha1511/Subckt_ICs
Subcircuits of different ICs (Contributor: Tanisha Tiwari)
Diffstat (limited to 'library/SubcircuitLibrary/CY74FCT480T/74480.cir')
| -rw-r--r-- | library/SubcircuitLibrary/CY74FCT480T/74480.cir | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/CY74FCT480T/74480.cir b/library/SubcircuitLibrary/CY74FCT480T/74480.cir new file mode 100644 index 00000000..41b94a89 --- /dev/null +++ b/library/SubcircuitLibrary/CY74FCT480T/74480.cir @@ -0,0 +1,32 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\74480\74480.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/20/25 19:44:02 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U4 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U10-Pad1_ d_xor +U5 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U10-Pad2_ d_xor +U6 Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U11-Pad1_ d_xor +U7 Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U11-Pad2_ d_xor +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_xor +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_xor +U14 Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U14-Pad3_ d_xor +U8 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U12-Pad1_ d_xor +U9 Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U12-Pad2_ d_xor +U2 Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U13-Pad1_ d_xor +U3 Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U13-Pad2_ d_xor +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_xor +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_xor +U15 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U15-Pad3_ d_xor +U20 Net-_U14-Pad3_ Net-_U18-Pad2_ Net-_U1-Pad20_ d_xor +U21 Net-_U15-Pad3_ Net-_U19-Pad2_ Net-_U1-Pad22_ d_xor +U22 Net-_U1-Pad20_ Net-_U1-Pad22_ Net-_U1-Pad21_ d_nor +U18 Net-_U16-Pad3_ Net-_U18-Pad2_ d_inverter +U16 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U16-Pad3_ d_and +U17 Net-_U1-Pad10_ Net-_U1-Pad19_ Net-_U17-Pad3_ d_and +U19 Net-_U17-Pad3_ Net-_U19-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ Net-_U1-Pad20_ Net-_U1-Pad21_ Net-_U1-Pad22_ PORT + +.end |