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authorAnkushECE2022-08-24 22:47:18 +0530
committerAnkushECE2022-08-24 22:47:18 +0530
commit0c8e849d3dc0fed85a8acf2193a6d5e6bd13cc5c (patch)
treeff28f2dca9da0fce6b2594fe6bc2045c150558e0 /library/SubcircuitLibrary/CD_4008/CD_4008.cir
parente89df49ea9ec469ad4a0a8745da1ffc5ba47bcf7 (diff)
downloadeSim-0c8e849d3dc0fed85a8acf2193a6d5e6bd13cc5c.tar.gz
eSim-0c8e849d3dc0fed85a8acf2193a6d5e6bd13cc5c.tar.bz2
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CD4008 is 4 bit Full Adder IC.
Diffstat (limited to 'library/SubcircuitLibrary/CD_4008/CD_4008.cir')
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diff --git a/library/SubcircuitLibrary/CD_4008/CD_4008.cir b/library/SubcircuitLibrary/CD_4008/CD_4008.cir
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+* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD_4008\CD_4008.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/02/22 20:13:23
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad16_ Net-_X1-Pad17_ Adder_2Bit
+X2 Net-_U1-Pad15_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad8_ Net-_X1-Pad17_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad16_ Net-_U1-Pad14_ Adder_2Bit
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ PORT
+
+.end