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authorSumanto Kar2025-02-23 17:20:17 +0530
committerGitHub2025-02-23 17:20:17 +0530
commitae99d42b8d2ffeaf91f96d5ffbe5efe91214cf0c (patch)
treee28be9a5dd152dd76d593ea9541d95305bbb059b /library/SubcircuitLibrary/CD4532B/4_and.cir.out
parent679e6ad8242e09d69576208c9fffaa3694a41b70 (diff)
parentb712ae83d0802e76c2760e49cc6c03b5eaa190dc (diff)
downloadeSim-ae99d42b8d2ffeaf91f96d5ffbe5efe91214cf0c.tar.gz
eSim-ae99d42b8d2ffeaf91f96d5ffbe5efe91214cf0c.tar.bz2
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Merge pull request #303 from Rachith-H/master
Subcircuit Files for different IC's
Diffstat (limited to 'library/SubcircuitLibrary/CD4532B/4_and.cir.out')
-rw-r--r--library/SubcircuitLibrary/CD4532B/4_and.cir.out18
1 files changed, 18 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/CD4532B/4_and.cir.out b/library/SubcircuitLibrary/CD4532B/4_and.cir.out
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+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end