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authorSumanto Kar2023-05-04 12:25:41 +0530
committerGitHub2023-05-04 12:25:41 +0530
commit4f21a7fa863aebf0d44af34417c341d6fc475052 (patch)
treec4b7cb04c78c1a334c963a1d4e4d5a6e43f19e58 /library/SubcircuitLibrary/CD4028_B/CD4028_B.sub
parentdbebfaea6ae619dfcbfe239bc2cdff07beb57857 (diff)
parent0fa7cd5ab4a888272d03ad47d0eabfc9095bbbbb (diff)
downloadeSim-4f21a7fa863aebf0d44af34417c341d6fc475052.tar.gz
eSim-4f21a7fa863aebf0d44af34417c341d6fc475052.tar.bz2
eSim-4f21a7fa863aebf0d44af34417c341d6fc475052.zip
Merge pull request #219 from AnkushECE/master
Sub circuit files for AD620, LM7809, LM386, CD40XX family and CD54HC15X MUX family
Diffstat (limited to 'library/SubcircuitLibrary/CD4028_B/CD4028_B.sub')
-rw-r--r--library/SubcircuitLibrary/CD4028_B/CD4028_B.sub35
1 files changed, 35 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/CD4028_B/CD4028_B.sub b/library/SubcircuitLibrary/CD4028_B/CD4028_B.sub
new file mode 100644
index 00000000..f43f7ea9
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4028_B/CD4028_B.sub
@@ -0,0 +1,35 @@
+* Subcircuit CD4028_B
+.subckt CD4028_B net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_m1-pad3_ net-_u1-pad9_ net-_m4-pad2_ net-_m3-pad2_ net-_m2-pad2_ net-_m1-pad2_ net-_u1-pad14_ net-_u1-pad15_ net-_m5-pad3_
+* c:\fossee\esim\library\subcircuitlibrary\cd4028_b\cd4028_b.cir
+.include AND_Gate.sub
+.include NOR_Gate.sub
+.include NMOS-180nm.lib
+.include PMOS-180nm.lib
+x5 net-_x12-pad2_ net-_m4-pad2_ net-_m1-pad2_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate
+x6 net-_x13-pad2_ net-_m4-pad1_ net-_m1-pad2_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate
+x7 net-_x10-pad2_ net-_m4-pad2_ net-_m1-pad1_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate
+x2 net-_x11-pad2_ net-_m4-pad1_ net-_m1-pad1_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate
+x1 net-_x1-pad1_ net-_m2-pad2_ net-_m3-pad2_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate
+x3 net-_x12-pad3_ net-_m2-pad1_ net-_m3-pad2_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate
+x4 net-_x16-pad3_ net-_m2-pad2_ net-_m3-pad1_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate
+x8 net-_u1-pad3_ net-_x12-pad2_ net-_x1-pad1_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate
+x9 net-_u1-pad14_ net-_x13-pad2_ net-_x1-pad1_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate
+x10 net-_u1-pad2_ net-_x10-pad2_ net-_x1-pad1_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate
+x11 net-_u1-pad15_ net-_x11-pad2_ net-_x1-pad1_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate
+x12 net-_u1-pad1_ net-_x12-pad2_ net-_x12-pad3_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate
+x13 net-_u1-pad6_ net-_x13-pad2_ net-_x12-pad3_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate
+x14 net-_u1-pad7_ net-_x10-pad2_ net-_x12-pad3_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate
+x15 net-_u1-pad4_ net-_x11-pad2_ net-_x12-pad3_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate
+x16 net-_u1-pad9_ net-_x12-pad2_ net-_x16-pad3_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate
+x17 net-_u1-pad5_ net-_x13-pad2_ net-_x16-pad3_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate
+m8 net-_m4-pad1_ net-_m4-pad2_ net-_m5-pad3_ net-_m5-pad3_ CMOSP W=100u L=100u M=1
+m4 net-_m4-pad1_ net-_m4-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m5 net-_m1-pad1_ net-_m1-pad2_ net-_m5-pad3_ net-_m5-pad3_ CMOSP W=100u L=100u M=1
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m6 net-_m2-pad1_ net-_m2-pad2_ net-_m5-pad3_ net-_m5-pad3_ CMOSP W=100u L=100u M=1
+m2 net-_m2-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m7 net-_m3-pad1_ net-_m3-pad2_ net-_m5-pad3_ net-_m5-pad3_ CMOSP W=100u L=100u M=1
+m3 net-_m3-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+* Control Statements
+
+.ends CD4028_B \ No newline at end of file