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| author | Sumanto Kar | 2023-05-04 13:13:01 +0530 |
|---|---|---|
| committer | GitHub | 2023-05-04 13:13:01 +0530 |
| commit | 57e699fdd79e8be77385bc2a4e017408e5d5afaa (patch) | |
| tree | 9a81f2090740d02ad33b29f5db49123995c0a41e /library/SubcircuitLibrary/CD4028_B/AND_Gate.cir | |
| parent | 427467420f97eef76fd0ecc067ebd426f5cac554 (diff) | |
| parent | 732e2c2a1b63b3af1f17a2f1a8c128db2a757b4c (diff) | |
| download | eSim-57e699fdd79e8be77385bc2a4e017408e5d5afaa.tar.gz eSim-57e699fdd79e8be77385bc2a4e017408e5d5afaa.tar.bz2 eSim-57e699fdd79e8be77385bc2a4e017408e5d5afaa.zip | |
Merge branch 'master' into master
Diffstat (limited to 'library/SubcircuitLibrary/CD4028_B/AND_Gate.cir')
| -rw-r--r-- | library/SubcircuitLibrary/CD4028_B/AND_Gate.cir | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/CD4028_B/AND_Gate.cir b/library/SubcircuitLibrary/CD4028_B/AND_Gate.cir new file mode 100644 index 00000000..17b9331f --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/AND_Gate.cir @@ -0,0 +1,17 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\AND_Gate\AND_Gate.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/26/22 14:03:16 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M2 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M2-Pad3_ Net-_M2-Pad3_ eSim_MOS_N +M4 Net-_M1-Pad1_ Net-_M3-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M3 Net-_M2-Pad3_ Net-_M3-Pad2_ Net-_M3-Pad3_ Net-_M3-Pad3_ eSim_MOS_N +M5 Net-_M5-Pad1_ Net-_M1-Pad1_ Net-_M3-Pad3_ Net-_M3-Pad3_ eSim_MOS_N +M6 Net-_M5-Pad1_ Net-_M1-Pad1_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +U1 Net-_M5-Pad1_ Net-_M1-Pad2_ Net-_M3-Pad2_ Net-_M1-Pad3_ Net-_M3-Pad3_ PORT + +.end |