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authorAditya Minocha2024-08-26 00:25:40 +0530
committerGitHub2024-08-26 00:25:40 +0530
commit044059f99adcc13c41252126c12cc6f7bbed6b5f (patch)
tree1204222bc15c9c0a8619411fb6cc9d070e045947 /library/SubcircuitLibrary/CD4027B_IC/NAND.cir
parentbd79f23e5034fd1a39a5d879057f842ae7747768 (diff)
downloadeSim-044059f99adcc13c41252126c12cc6f7bbed6b5f.tar.gz
eSim-044059f99adcc13c41252126c12cc6f7bbed6b5f.tar.bz2
eSim-044059f99adcc13c41252126c12cc6f7bbed6b5f.zip
CD4027B - CMOS Dual JK Flip Flop (failed)
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+* C:\FOSSEE\eSim\library\SubcircuitLibrary\NAND\NAND.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/28/24 22:27:04
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+M3 Net-_M2-Pad3_ Net-_M3-Pad2_ Net-_M3-Pad3_ Net-_M3-Pad3_ mosfet_n
+M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad1_ mosfet_p
+M4 Net-_M1-Pad1_ Net-_M3-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad1_ mosfet_p
+M2 Net-_M1-Pad3_ Net-_M1-Pad2_ Net-_M2-Pad3_ Net-_M2-Pad3_ mosfet_n
+U1 Net-_M1-Pad2_ Net-_M3-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad1_ Net-_M3-Pad3_ PORT
+
+.end