diff options
| author | Sumanto Kar | 2024-09-13 00:56:30 +0530 |
|---|---|---|
| committer | GitHub | 2024-09-13 00:56:30 +0530 |
| commit | 681978c7ce1aedee54b0ce6601b789edca226395 (patch) | |
| tree | fc4b37265699872bd87d9119e5334e9812a86f16 /library/SubcircuitLibrary/CD4027B_IC/Buffer.bak | |
| parent | 5f80292f451abd9c96849a277ec46670cd1446bc (diff) | |
| parent | 044059f99adcc13c41252126c12cc6f7bbed6b5f (diff) | |
| download | eSim-681978c7ce1aedee54b0ce6601b789edca226395.tar.gz eSim-681978c7ce1aedee54b0ce6601b789edca226395.tar.bz2 eSim-681978c7ce1aedee54b0ce6601b789edca226395.zip | |
Merge pull request #279 from AdityaMino/Aditya-Minocha
Subcircuit Files of ICs(Contributor: Aditya Minocha)
Diffstat (limited to 'library/SubcircuitLibrary/CD4027B_IC/Buffer.bak')
| -rw-r--r-- | library/SubcircuitLibrary/CD4027B_IC/Buffer.bak | 106 |
1 files changed, 106 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/CD4027B_IC/Buffer.bak b/library/SubcircuitLibrary/CD4027B_IC/Buffer.bak new file mode 100644 index 00000000..e193ba4c --- /dev/null +++ b/library/SubcircuitLibrary/CD4027B_IC/Buffer.bak @@ -0,0 +1,106 @@ +EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L NOT_Gate X1
+U 1 1 66559010
+P 3600 3650
+F 0 "X1" H 4200 3450 60 0000 C CNN
+F 1 "NOT_Gate" H 4250 3850 60 0000 C CNN
+F 2 "" H 3600 3650 60 0001 C CNN
+F 3 "" H 3600 3650 60 0001 C CNN
+ 1 3600 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L NOT_Gate X2
+U 1 1 66559039
+P 4650 3650
+F 0 "X2" H 5250 3450 60 0000 C CNN
+F 1 "NOT_Gate" H 5300 3850 60 0000 C CNN
+F 2 "" H 4650 3650 60 0001 C CNN
+F 3 "" H 4650 3650 60 0001 C CNN
+ 1 4650 3650
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5000 3650 4650 3650
+Wire Wire Line
+ 5700 3650 6100 3650
+Wire Wire Line
+ 3950 3650 3650 3650
+$Comp
+L PORT U1
+U 1 1 6655907A
+P 3400 3650
+F 0 "U1" H 3450 3750 30 0000 C CNN
+F 1 "PORT" H 3400 3650 30 0000 C CNN
+F 2 "" H 3400 3650 60 0000 C CNN
+F 3 "" H 3400 3650 60 0000 C CNN
+ 1 3400 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 665590B5
+P 6350 3650
+F 0 "U1" H 6400 3750 30 0000 C CNN
+F 1 "PORT" H 6350 3650 30 0000 C CNN
+F 2 "" H 6350 3650 60 0000 C CNN
+F 3 "" H 6350 3650 60 0000 C CNN
+ 2 6350 3650
+ -1 0 0 -1
+$EndComp
+$EndSCHEMATC
|