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| author | Aditya Minocha | 2024-08-25 18:50:30 +0530 |
|---|---|---|
| committer | GitHub | 2024-08-25 18:50:30 +0530 |
| commit | b95d015bd1b09a444b9297625c3290ab105517ac (patch) | |
| tree | b611059aa0c227baddacf1b92a9f4a4797bcdbff /library/SubcircuitLibrary/9348/NOT.cir | |
| parent | 7bc70caee91be4bc9d9a5c9de60f0260a1f968ae (diff) | |
| download | eSim-b95d015bd1b09a444b9297625c3290ab105517ac.tar.gz eSim-b95d015bd1b09a444b9297625c3290ab105517ac.tar.bz2 eSim-b95d015bd1b09a444b9297625c3290ab105517ac.zip | |
IC 9348 - 12 Input Parity Generator/Checker
Diffstat (limited to 'library/SubcircuitLibrary/9348/NOT.cir')
| -rw-r--r-- | library/SubcircuitLibrary/9348/NOT.cir | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/9348/NOT.cir b/library/SubcircuitLibrary/9348/NOT.cir new file mode 100644 index 00000000..074b85b3 --- /dev/null +++ b/library/SubcircuitLibrary/9348/NOT.cir @@ -0,0 +1,13 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\NOT\NOT.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/28/24 22:41:58
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ mosfet_n
+M2 Net-_M2-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad1_ Net-_M2-Pad1_ mosfet_p
+U1 Net-_M1-Pad2_ Net-_M1-Pad1_ Net-_M2-Pad1_ Net-_M1-Pad3_ PORT
+
+.end
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