Merge pull request #340 from CodeByHarshal/contrib-new-subckts

Subckt files for different ICs

8 files changed, 1208 insertions, 0 deletions

diff --git a/library/SubcircuitLibrary/74LS95B/74LS95B-cache.lib b/library/SubcircuitLibrary/74LS95B/74LS95B-cache.lib
new file mode 100644
index 00000000..340f2a85
--- /dev/null
+++ b/library/SubcircuitLibrary/74LS95B/74LS95B-cache.lib
@@ -0,0 +1,132 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 P
+X ~ 2 250 0 100 L 30 30 2 1 P
+X ~ 3 250 0 100 L 30 30 3 1 P
+X ~ 4 250 0 100 L 30 30 4 1 P
+X ~ 5 250 0 100 L 30 30 5 1 P
+X ~ 6 250 0 100 L 30 30 6 1 P
+X ~ 7 250 0 100 L 30 30 7 1 P
+X ~ 8 250 0 100 L 30 30 8 1 P
+X ~ 9 250 0 100 L 30 30 9 1 P
+X ~ 10 250 0 100 L 30 30 10 1 P
+X ~ 11 250 0 100 L 30 30 11 1 P
+X ~ 12 250 0 100 L 30 30 12 1 P
+X ~ 13 250 0 100 L 30 30 13 1 P
+X ~ 14 250 0 100 L 30 30 14 1 P
+X ~ 15 250 0 100 L 30 30 15 1 P
+X ~ 16 250 0 100 L 30 30 16 1 P
+X ~ 17 250 0 100 L 30 30 17 1 P
+X ~ 18 250 0 100 L 30 30 18 1 P
+X ~ 19 250 0 100 L 30 30 19 1 P
+X ~ 20 250 0 100 L 30 30 20 1 P
+X ~ 21 250 0 100 L 30 30 21 1 P
+X ~ 22 250 0 100 L 30 30 22 1 P
+X ~ 23 250 0 100 L 30 30 23 1 P
+X ~ 24 250 0 100 L 30 30 24 1 P
+X ~ 25 250 0 100 L 30 30 25 1 P
+X ~ 26 250 0 100 L 30 30 26 1 P
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_srff
+#
+DEF d_srff U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_srff" 50 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S 600 550 -600 -600 0 1 0 N
+X S 1 -800 400 200 R 50 50 1 1 I
+X R 2 -800 -450 200 R 50 50 1 1 I
+X Clk 3 -800 0 200 R 50 50 1 1 I C
+X Set 4 0 750 200 D 50 50 1 1 I
+X Reset 5 0 -800 200 U 50 50 1 1 I
+X Out 6 800 400 200 L 50 50 1 1 O
+X Nout 7 800 -450 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74LS95B/74LS95B.cir b/library/SubcircuitLibrary/74LS95B/74LS95B.cir
new file mode 100644
index 00000000..edb7331b
--- /dev/null
+++ b/library/SubcircuitLibrary/74LS95B/74LS95B.cir
@@ -0,0 +1,36 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\74LS95B\74LS95B.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/23/25 17:25:00
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U11  Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ Net-_U1-Pad14_ /VCC /Q0 ? d_srff		
+U21  Net-_U19-Pad2_ Net-_U18-Pad3_ Net-_U11-Pad3_ Net-_U1-Pad14_ /VCC /Q2 ? d_srff		
+U26  Net-_U24-Pad2_ Net-_U23-Pad3_ Net-_U11-Pad3_ Net-_U1-Pad14_ /VCC /Q3 ? d_srff		
+U6  Net-_U3-Pad3_ Net-_U4-Pad3_ Net-_U11-Pad3_ d_or		
+U3  Net-_U12-Pad2_ /CP1 Net-_U3-Pad3_ d_and		
+U4  /S /CP2 Net-_U4-Pad3_ d_and		
+U8  Net-_U10-Pad3_ Net-_U7-Pad3_ Net-_U11-Pad2_ d_nor		
+U7  /Ds Net-_U12-Pad2_ Net-_U7-Pad3_ d_and		
+U10  Net-_U10-Pad1_ /P0 Net-_U10-Pad3_ d_and		
+U13  Net-_U13-Pad1_ Net-_U12-Pad3_ Net-_U13-Pad3_ d_nor		
+U12  /Q0 Net-_U12-Pad2_ Net-_U12-Pad3_ d_and		
+U15  Net-_U10-Pad1_ /P1 Net-_U13-Pad1_ d_and		
+U18  Net-_U18-Pad1_ Net-_U17-Pad3_ Net-_U18-Pad3_ d_nor		
+U17  /Q1 Net-_U12-Pad2_ Net-_U17-Pad3_ d_and		
+U20  Net-_U10-Pad1_ /P2 Net-_U18-Pad1_ d_and		
+U23  Net-_U23-Pad1_ Net-_U22-Pad3_ Net-_U23-Pad3_ d_nor		
+U22  /Q2 Net-_U12-Pad2_ Net-_U22-Pad3_ d_and		
+U25  Net-_U10-Pad1_ /P3 Net-_U23-Pad1_ d_and		
+U9  Net-_U11-Pad2_ Net-_U11-Pad1_ d_inverter		
+U14  Net-_U13-Pad3_ Net-_U14-Pad2_ d_inverter		
+U19  Net-_U18-Pad3_ Net-_U19-Pad2_ d_inverter		
+U24  Net-_U23-Pad3_ Net-_U24-Pad2_ d_inverter		
+U2  /S Net-_U12-Pad2_ d_inverter		
+U5  Net-_U12-Pad2_ Net-_U10-Pad1_ d_inverter		
+U1  /Ds /P0 /P1 /P2 /P3 /S /VCC /CP2 /CP1 /Q3 /Q2 /Q1 /Q0 Net-_U1-Pad14_ PORT		
+U16  Net-_U14-Pad2_ Net-_U13-Pad3_ Net-_U11-Pad3_ Net-_U1-Pad14_ /VCC /Q1 ? d_srff		
+
+.end
diff --git a/library/SubcircuitLibrary/74LS95B/74LS95B.cir.out b/library/SubcircuitLibrary/74LS95B/74LS95B.cir.out
new file mode 100644
index 00000000..647f9803
--- /dev/null
+++ b/library/SubcircuitLibrary/74LS95B/74LS95B.cir.out
@@ -0,0 +1,112 @@
+* c:\fossee\esim\library\subcircuitlibrary\74ls95b\74ls95b.cir
+
+* u11  net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ net-_u1-pad14_ /vcc /q0 ? d_srff
+* u21  net-_u19-pad2_ net-_u18-pad3_ net-_u11-pad3_ net-_u1-pad14_ /vcc /q2 ? d_srff
+* u26  net-_u24-pad2_ net-_u23-pad3_ net-_u11-pad3_ net-_u1-pad14_ /vcc /q3 ? d_srff
+* u6  net-_u3-pad3_ net-_u4-pad3_ net-_u11-pad3_ d_or
+* u3  net-_u12-pad2_ /cp1 net-_u3-pad3_ d_and
+* u4  /s /cp2 net-_u4-pad3_ d_and
+* u8  net-_u10-pad3_ net-_u7-pad3_ net-_u11-pad2_ d_nor
+* u7  /ds net-_u12-pad2_ net-_u7-pad3_ d_and
+* u10  net-_u10-pad1_ /p0 net-_u10-pad3_ d_and
+* u13  net-_u13-pad1_ net-_u12-pad3_ net-_u13-pad3_ d_nor
+* u12  /q0 net-_u12-pad2_ net-_u12-pad3_ d_and
+* u15  net-_u10-pad1_ /p1 net-_u13-pad1_ d_and
+* u18  net-_u18-pad1_ net-_u17-pad3_ net-_u18-pad3_ d_nor
+* u17  /q1 net-_u12-pad2_ net-_u17-pad3_ d_and
+* u20  net-_u10-pad1_ /p2 net-_u18-pad1_ d_and
+* u23  net-_u23-pad1_ net-_u22-pad3_ net-_u23-pad3_ d_nor
+* u22  /q2 net-_u12-pad2_ net-_u22-pad3_ d_and
+* u25  net-_u10-pad1_ /p3 net-_u23-pad1_ d_and
+* u9  net-_u11-pad2_ net-_u11-pad1_ d_inverter
+* u14  net-_u13-pad3_ net-_u14-pad2_ d_inverter
+* u19  net-_u18-pad3_ net-_u19-pad2_ d_inverter
+* u24  net-_u23-pad3_ net-_u24-pad2_ d_inverter
+* u2  /s net-_u12-pad2_ d_inverter
+* u5  net-_u12-pad2_ net-_u10-pad1_ d_inverter
+* u1  /ds /p0 /p1 /p2 /p3 /s /vcc /cp2 /cp1 /q3 /q2 /q1 /q0 net-_u1-pad14_ port
+* u16  net-_u14-pad2_ net-_u13-pad3_ net-_u11-pad3_ net-_u1-pad14_ /vcc /q1 ? d_srff
+a1 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ net-_u1-pad14_ /vcc /q0 ? u11
+a2 net-_u19-pad2_ net-_u18-pad3_ net-_u11-pad3_ net-_u1-pad14_ /vcc /q2 ? u21
+a3 net-_u24-pad2_ net-_u23-pad3_ net-_u11-pad3_ net-_u1-pad14_ /vcc /q3 ? u26
+a4 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u11-pad3_ u6
+a5 [net-_u12-pad2_ /cp1 ] net-_u3-pad3_ u3
+a6 [/s /cp2 ] net-_u4-pad3_ u4
+a7 [net-_u10-pad3_ net-_u7-pad3_ ] net-_u11-pad2_ u8
+a8 [/ds net-_u12-pad2_ ] net-_u7-pad3_ u7
+a9 [net-_u10-pad1_ /p0 ] net-_u10-pad3_ u10
+a10 [net-_u13-pad1_ net-_u12-pad3_ ] net-_u13-pad3_ u13
+a11 [/q0 net-_u12-pad2_ ] net-_u12-pad3_ u12
+a12 [net-_u10-pad1_ /p1 ] net-_u13-pad1_ u15
+a13 [net-_u18-pad1_ net-_u17-pad3_ ] net-_u18-pad3_ u18
+a14 [/q1 net-_u12-pad2_ ] net-_u17-pad3_ u17
+a15 [net-_u10-pad1_ /p2 ] net-_u18-pad1_ u20
+a16 [net-_u23-pad1_ net-_u22-pad3_ ] net-_u23-pad3_ u23
+a17 [/q2 net-_u12-pad2_ ] net-_u22-pad3_ u22
+a18 [net-_u10-pad1_ /p3 ] net-_u23-pad1_ u25
+a19 net-_u11-pad2_ net-_u11-pad1_ u9
+a20 net-_u13-pad3_ net-_u14-pad2_ u14
+a21 net-_u18-pad3_ net-_u19-pad2_ u19
+a22 net-_u23-pad3_ net-_u24-pad2_ u24
+a23 /s net-_u12-pad2_ u2
+a24 net-_u12-pad2_ net-_u10-pad1_ u5
+a25 net-_u14-pad2_ net-_u13-pad3_ net-_u11-pad3_ net-_u1-pad14_ /vcc /q1 ? u16
+* Schematic Name:                             d_srff, NgSpice Name: d_srff
+.model u11 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_srff, NgSpice Name: d_srff
+.model u21 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_srff, NgSpice Name: d_srff
+.model u26 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u6 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u8 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u13 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u18 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u23 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_srff, NgSpice Name: d_srff
+.model u16 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74LS95B/74LS95B.pro b/library/SubcircuitLibrary/74LS95B/74LS95B.pro
new file mode 100644
index 00000000..e3dbe802
--- /dev/null
+++ b/library/SubcircuitLibrary/74LS95B/74LS95B.pro
@@ -0,0 +1,83 @@
+update=03/18/25 10:43:53
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=Spice
+SpiceForceRefPrefix=0
+SpiceUseNetNumbers=0
+LabSize=60
diff --git a/library/SubcircuitLibrary/74LS95B/74LS95B.sch b/library/SubcircuitLibrary/74LS95B/74LS95B.sch
new file mode 100644
index 00000000..22b21dc8
--- /dev/null
+++ b/library/SubcircuitLibrary/74LS95B/74LS95B.sch
@@ -0,0 +1,737 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:74LS95B-cache
+EELAYER 25 0
+EELAYER END
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+encoding utf-8
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+F 3 "" H 3850 5300 60  0000 C CNN
+	1    3850 5300
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+$EndComp
+$Comp
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+F 2 "" H 7900 5300 60  0000 C CNN
+F 3 "" H 7900 5300 60  0000 C CNN
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+F 2 "" H 9950 5300 60  0000 C CNN
+F 3 "" H 9950 5300 60  0000 C CNN
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+F 1 "d_or" H 2300 4250 60  0000 C CNN
+F 2 "" H 2300 4150 60  0000 C CNN
+F 3 "" H 2300 4150 60  0000 C CNN
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+	1    0    0    -1  
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+F 1 "d_and" H 1450 4050 60  0000 C CNN
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+F 3 "" H 1400 3950 60  0000 C CNN
+	1    1400 3950
+	1    0    0    -1  
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+F 3 "" H 1400 4300 60  0000 C CNN
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+F 3 "" H 2750 2850 60  0000 C CNN
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+F 2 "" H 2700 1950 60  0000 C CNN
+F 3 "" H 2700 1950 60  0000 C CNN
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+F 3 "" H 3000 1950 60  0000 C CNN
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+F 2 "" H 4850 2850 60  0000 C CNN
+F 3 "" H 4850 2850 60  0000 C CNN
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+F 2 "" H 4800 1950 60  0000 C CNN
+F 3 "" H 4800 1950 60  0000 C CNN
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+F 1 "d_and" H 5150 2050 60  0000 C CNN
+F 2 "" H 5100 1950 60  0000 C CNN
+F 3 "" H 5100 1950 60  0000 C CNN
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+	0    -1   1    0   
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+F 1 "d_nor" H 6950 2950 60  0000 C CNN
+F 2 "" H 6900 2850 60  0000 C CNN
+F 3 "" H 6900 2850 60  0000 C CNN
+	1    6900 2850
+	0    1    1    0   
+$EndComp
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+U 1 1 67D8FB0B
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+F 0 "U17" H 6850 1950 60  0000 C CNN
+F 1 "d_and" H 6900 2050 60  0000 C CNN
+F 2 "" H 6850 1950 60  0000 C CNN
+F 3 "" H 6850 1950 60  0000 C CNN
+	1    6850 1950
+	0    -1   1    0   
+$EndComp
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+L d_and U20
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+P 7150 1950
+F 0 "U20" H 7150 1950 60  0000 C CNN
+F 1 "d_and" H 7200 2050 60  0000 C CNN
+F 2 "" H 7150 1950 60  0000 C CNN
+F 3 "" H 7150 1950 60  0000 C CNN
+	1    7150 1950
+	0    -1   1    0   
+$EndComp
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+L d_nor U23
+U 1 1 67D8FB0D
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+F 0 "U23" H 8900 2850 60  0000 C CNN
+F 1 "d_nor" H 8950 2950 60  0000 C CNN
+F 2 "" H 8900 2850 60  0000 C CNN
+F 3 "" H 8900 2850 60  0000 C CNN
+	1    8900 2850
+	0    1    1    0   
+$EndComp
+$Comp
+L d_and U22
+U 1 1 67D8FB0E
+P 8850 1950
+F 0 "U22" H 8850 1950 60  0000 C CNN
+F 1 "d_and" H 8900 2050 60  0000 C CNN
+F 2 "" H 8850 1950 60  0000 C CNN
+F 3 "" H 8850 1950 60  0000 C CNN
+	1    8850 1950
+	0    -1   1    0   
+$EndComp
+$Comp
+L d_and U25
+U 1 1 67D8FB0F
+P 9150 1950
+F 0 "U25" H 9150 1950 60  0000 C CNN
+F 1 "d_and" H 9200 2050 60  0000 C CNN
+F 2 "" H 9150 1950 60  0000 C CNN
+F 3 "" H 9150 1950 60  0000 C CNN
+	1    9150 1950
+	0    -1   1    0   
+$EndComp
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+L d_inverter U9
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+P 2800 5400
+F 0 "U9" H 2800 5300 60  0000 C CNN
+F 1 "d_inverter" H 2800 5550 60  0000 C CNN
+F 2 "" H 2850 5350 60  0000 C CNN
+F 3 "" H 2850 5350 60  0000 C CNN
+	1    2800 5400
+	0    1    1    0   
+$EndComp
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+L d_inverter U14
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+F 0 "U14" H 4900 5250 60  0000 C CNN
+F 1 "d_inverter" H 4900 5500 60  0000 C CNN
+F 2 "" H 4950 5300 60  0000 C CNN
+F 3 "" H 4950 5300 60  0000 C CNN
+	1    4900 5350
+	0    1    1    0   
+$EndComp
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+L d_inverter U19
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+F 0 "U19" H 6900 5300 60  0000 C CNN
+F 1 "d_inverter" H 6900 5550 60  0000 C CNN
+F 2 "" H 6950 5350 60  0000 C CNN
+F 3 "" H 6950 5350 60  0000 C CNN
+	1    6900 5400
+	0    1    1    0   
+$EndComp
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+L d_inverter U24
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+P 8950 5400
+F 0 "U24" H 8950 5300 60  0000 C CNN
+F 1 "d_inverter" H 8950 5550 60  0000 C CNN
+F 2 "" H 9000 5350 60  0000 C CNN
+F 3 "" H 9000 5350 60  0000 C CNN
+	1    8950 5400
+	0    1    1    0   
+$EndComp
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+F 1 "d_inverter" H 1300 1250 60  0000 C CNN
+F 2 "" H 1350 1050 60  0000 C CNN
+F 3 "" H 1350 1050 60  0000 C CNN
+	1    1300 1100
+	1    0    0    -1  
+$EndComp
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+L d_inverter U5
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+F 0 "U5" H 2050 1000 60  0000 C CNN
+F 1 "d_inverter" H 2050 1250 60  0000 C CNN
+F 2 "" H 2100 1050 60  0000 C CNN
+F 3 "" H 2100 1050 60  0000 C CNN
+	1    2050 1100
+	1    0    0    -1  
+$EndComp
+Text Label 10000 4500 0    60   ~ 0
+VCC
+Text Label 4700 6300 0    60   ~ 0
+Q0
+Text Label 8700 6200 0    60   ~ 0
+Q2
+Text Label 10850 6100 0    60   ~ 0
+Q3
+Text Label 3000 950  0    60   ~ 0
+P0
+Text Label 5100 900  0    60   ~ 0
+P1
+Text Label 7150 850  0    60   ~ 0
+P2
+Text Label 9150 950  0    60   ~ 0
+P3
+Text Label 1350 1500 0    60   ~ 0
+Ds
+Text Label 700  1100 0    60   ~ 0
+S
+Text Label 850  3950 0    60   ~ 0
+CP1
+Text Label 750  4300 0    60   ~ 0
+CP2
+$Comp
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+P 1150 1850
+F 0 "U1" H 1200 1950 30  0000 C CNN
+F 1 "PORT" H 1150 1850 30  0000 C CNN
+F 2 "" H 1150 1850 60  0000 C CNN
+F 3 "" H 1150 1850 60  0000 C CNN
+	1    1150 1850
+	0    1    -1   0   
+$EndComp
+$Comp
+L PORT U1
+U 2 1 67D8FFAD
+P 3400 750
+F 0 "U1" H 3450 850 30  0000 C CNN
+F 1 "PORT" H 3400 750 30  0000 C CNN
+F 2 "" H 3400 750 60  0000 C CNN
+F 3 "" H 3400 750 60  0000 C CNN
+	2    3400 750 
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 67D90179
+P 5500 700
+F 0 "U1" H 5550 800 30  0000 C CNN
+F 1 "PORT" H 5500 700 30  0000 C CNN
+F 2 "" H 5500 700 60  0000 C CNN
+F 3 "" H 5500 700 60  0000 C CNN
+	3    5500 700 
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 67D9036E
+P 7550 700
+F 0 "U1" H 7600 800 30  0000 C CNN
+F 1 "PORT" H 7550 700 30  0000 C CNN
+F 2 "" H 7550 700 60  0000 C CNN
+F 3 "" H 7550 700 60  0000 C CNN
+	4    7550 700 
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 67D905AD
+P 9550 750
+F 0 "U1" H 9600 850 30  0000 C CNN
+F 1 "PORT" H 9550 750 30  0000 C CNN
+F 2 "" H 9550 750 60  0000 C CNN
+F 3 "" H 9550 750 60  0000 C CNN
+	5    9550 750 
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 6 1 67D908EC
+P 650 800
+F 0 "U1" H 700 900 30  0000 C CNN
+F 1 "PORT" H 650 800 30  0000 C CNN
+F 2 "" H 650 800 60  0000 C CNN
+F 3 "" H 650 800 60  0000 C CNN
+	6    650  800 
+	0    -1   1    0   
+$EndComp
+$Comp
+L PORT U1
+U 8 1 67D910F2
+P 650 4650
+F 0 "U1" H 700 4750 30  0000 C CNN
+F 1 "PORT" H 650 4650 30  0000 C CNN
+F 2 "" H 650 4650 60  0000 C CNN
+F 3 "" H 650 4650 60  0000 C CNN
+	8    650  4650
+	0    1    -1   0   
+$EndComp
+$Comp
+L PORT U1
+U 9 1 67D91351
+P 650 3650
+F 0 "U1" H 700 3750 30  0000 C CNN
+F 1 "PORT" H 650 3650 30  0000 C CNN
+F 2 "" H 650 3650 60  0000 C CNN
+F 3 "" H 650 3650 60  0000 C CNN
+	9    650  3650
+	0    1    1    0   
+$EndComp
+$Comp
+L PORT U1
+U 10 1 67D917FF
+P 10450 6250
+F 0 "U1" H 10500 6350 30  0000 C CNN
+F 1 "PORT" H 10450 6250 30  0000 C CNN
+F 2 "" H 10450 6250 60  0000 C CNN
+F 3 "" H 10450 6250 60  0000 C CNN
+	10   10450 6250
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 11 1 67D9197F
+P 9050 6400
+F 0 "U1" H 9100 6500 30  0000 C CNN
+F 1 "PORT" H 9050 6400 30  0000 C CNN
+F 2 "" H 9050 6400 60  0000 C CNN
+F 3 "" H 9050 6400 60  0000 C CNN
+	11   9050 6400
+	-1   0    0    -1  
+$EndComp
+Text Label 6750 6300 0    60   ~ 0
+Q1
+$Comp
+L PORT U1
+U 12 1 67D92494
+P 7450 6250
+F 0 "U1" H 7500 6350 30  0000 C CNN
+F 1 "PORT" H 7450 6250 30  0000 C CNN
+F 2 "" H 7450 6250 60  0000 C CNN
+F 3 "" H 7450 6250 60  0000 C CNN
+	12   7450 6250
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 13 1 67D927C8
+P 5050 6450
+F 0 "U1" H 5100 6550 30  0000 C CNN
+F 1 "PORT" H 5050 6450 30  0000 C CNN
+F 2 "" H 5050 6450 60  0000 C CNN
+F 3 "" H 5050 6450 60  0000 C CNN
+	13   5050 6450
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 14 1 67D92A4C
+P 3600 6050
+F 0 "U1" H 3650 6150 30  0000 C CNN
+F 1 "PORT" H 3600 6050 30  0000 C CNN
+F 2 "" H 3600 6050 60  0000 C CNN
+F 3 "" H 3600 6050 60  0000 C CNN
+	14   3600 6050
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_srff U16
+U 1 1 67D8FAFE
+P 5950 5300
+F 0 "U16" H 5950 5300 60  0000 C CNN
+F 1 "d_srff" H 6000 5450 60  0000 C CNN
+F 2 "" H 5950 5300 60  0000 C CNN
+F 3 "" H 5950 5300 60  0000 C CNN
+	1    5950 5300
+	1    0    0    1   
+$EndComp
+Wire Wire Line
+	1850 3900 1850 4050
+Wire Wire Line
+	1850 4250 1850 4150
+Wire Wire Line
+	2750 4100 9150 4100
+Wire Wire Line
+	9100 5300 9150 5300
+Wire Wire Line
+	2650 2400 2750 2400
+Wire Wire Line
+	2850 2400 2950 2400
+Wire Wire Line
+	4750 2400 4850 2400
+Wire Wire Line
+	4950 2400 5050 2400
+Wire Wire Line
+	6800 2400 6900 2400
+Wire Wire Line
+	7000 2400 7100 2400
+Wire Wire Line
+	8800 2400 8900 2400
+Wire Wire Line
+	9000 2400 9100 2400
+Wire Wire Line
+	2800 3300 2800 5100
+Wire Wire Line
+	2800 5700 3050 5700
+Wire Wire Line
+	4900 3300 4900 5050
+Wire Wire Line
+	4900 5650 4900 5700
+Wire Wire Line
+	4900 5700 5150 5700
+Wire Wire Line
+	7100 5700 6900 5700
+Wire Wire Line
+	6900 3400 6900 5100
+Wire Wire Line
+	6900 3400 6950 3400
+Wire Wire Line
+	6950 3400 6950 3300
+Wire Wire Line
+	8950 3300 8950 5100
+Wire Wire Line
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+Wire Wire Line
+	9100 5300 9100 4200
+Wire Wire Line
+	9100 4200 9150 4200
+Wire Wire Line
+	9150 4200 9150 4100
+Wire Wire Line
+	7100 5300 7100 5100
+Wire Wire Line
+	7100 5100 7000 5100
+Connection ~ 7000 4100
+Wire Wire Line
+	7000 5100 7000 4100
+Wire Wire Line
+	7100 4850 6900 4850
+Connection ~ 6900 4850
+Wire Wire Line
+	5150 5300 5150 5000
+Wire Wire Line
+	5150 5000 5050 5000
+Wire Wire Line
+	5050 5000 5050 4100
+Connection ~ 5050 4100
+Wire Wire Line
+	5150 4850 4900 4850
+Connection ~ 4900 4850
+Wire Wire Line
+	3050 5300 3050 5050
+Wire Wire Line
+	3050 5050 2950 5050
+Wire Wire Line
+	2950 5050 2950 4100
+Connection ~ 2950 4100
+Wire Wire Line
+	3050 4850 2800 4850
+Connection ~ 2800 4850
+Wire Wire Line
+	2350 1100 9050 1100
+Wire Wire Line
+	9050 1100 9050 1500
+Wire Wire Line
+	7050 1500 7050 1100
+Connection ~ 7050 1100
+Wire Wire Line
+	5000 1500 5000 1100
+Connection ~ 5000 1100
+Wire Wire Line
+	2900 1500 2900 1100
+Connection ~ 2900 1100
+Wire Wire Line
+	1600 1100 1750 1100
+Wire Wire Line
+	650  1100 1000 1100
+Wire Wire Line
+	950  3850 950  3700
+Wire Wire Line
+	950  4200 800  4200
+Wire Wire Line
+	800  4200 800  1100
+Connection ~ 800  1100
+Wire Wire Line
+	1650 1100 1650 3700
+Wire Wire Line
+	1650 3700 950  3700
+Connection ~ 1650 1100
+Wire Wire Line
+	1650 1350 8850 1350
+Wire Wire Line
+	8850 1350 8850 1500
+Connection ~ 1650 1350
+Wire Wire Line
+	6850 1500 6850 1350
+Connection ~ 6850 1350
+Wire Wire Line
+	4800 1500 4800 1350
+Connection ~ 4800 1350
+Wire Wire Line
+	2700 1500 2700 1350
+Connection ~ 2700 1350
+Wire Wire Line
+	4700 3700 4700 6450
+Wire Wire Line
+	4650 5700 4700 5700
+Connection ~ 4700 5700
+Wire Wire Line
+	6500 4650 6850 4650
+Wire Wire Line
+	6850 4650 6850 5100
+Wire Wire Line
+	6850 5100 6750 5100
+Wire Wire Line
+	8750 1500 8550 1500
+Wire Wire Line
+	8550 1500 8550 3800
+Wire Wire Line
+	8550 3800 8850 3800
+Wire Wire Line
+	8850 3800 8850 5250
+Wire Wire Line
+	8850 5250 8700 5250
+Wire Wire Line
+	8700 5250 8700 6400
+Connection ~ 8700 5700
+Wire Wire Line
+	10750 5700 10850 5700
+Wire Wire Line
+	10850 5700 10850 6250
+Wire Wire Line
+	3850 6050 9950 6050
+Connection ~ 7900 6050
+Connection ~ 5950 6050
+Connection ~ 3850 6050
+Wire Wire Line
+	3000 1500 3000 750 
+Wire Wire Line
+	5100 1500 5100 700 
+Wire Wire Line
+	7150 1500 7150 700 
+Wire Wire Line
+	9150 1500 9150 750 
+Wire Wire Line
+	1150 1500 2600 1500
+Wire Wire Line
+	950  3950 650  3950
+Wire Wire Line
+	950  4300 650  4300
+Wire Wire Line
+	9150 4850 8950 4850
+Connection ~ 8950 4850
+Wire Wire Line
+	1150 1600 1150 1500
+Wire Wire Line
+	3000 750  3150 750 
+Wire Wire Line
+	5100 700  5250 700 
+Wire Wire Line
+	7150 700  7300 700 
+Wire Wire Line
+	9150 750  9300 750 
+Wire Wire Line
+	650  1100 650  1050
+Wire Wire Line
+	650  4300 650  4400
+Wire Wire Line
+	650  3950 650  3900
+Wire Wire Line
+	10850 6250 10700 6250
+Wire Wire Line
+	8700 6400 8800 6400
+Wire Wire Line
+	6750 5100 6750 6450
+Connection ~ 6750 5700
+Wire Wire Line
+	6750 6450 7000 6450
+Wire Wire Line
+	7000 6450 7000 6250
+Wire Wire Line
+	7000 6250 7200 6250
+Wire Wire Line
+	4700 6450 4800 6450
+Wire Wire Line
+	6500 4650 6500 1500
+Wire Wire Line
+	6500 1500 6750 1500
+Wire Wire Line
+	4700 3700 4450 3700
+Wire Wire Line
+	4450 3700 4450 1500
+Wire Wire Line
+	4450 1500 4700 1500
+NoConn ~ 4650 4850
+NoConn ~ 6750 4850
+NoConn ~ 8700 4850
+NoConn ~ 10750 4850
+Wire Wire Line
+	3850 4500 10125 4500
+Connection ~ 5950 4500
+Connection ~ 7900 4500
+Connection ~ 9950 4500
+$Comp
+L PORT U1
+U 7 1 67E00190
+P 10375 4500
+F 0 "U1" H 10425 4600 30  0000 C CNN
+F 1 "PORT" H 10375 4500 30  0000 C CNN
+F 2 "" H 10375 4500 60  0000 C CNN
+F 3 "" H 10375 4500 60  0000 C CNN
+	7    10375 4500
+	-1   0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74LS95B/74LS95B.sub b/library/SubcircuitLibrary/74LS95B/74LS95B.sub
new file mode 100644
index 00000000..5d893f01
--- /dev/null
+++ b/library/SubcircuitLibrary/74LS95B/74LS95B.sub
@@ -0,0 +1,106 @@
+* Subcircuit 74LS95B
+.subckt 74LS95B /ds /p0 /p1 /p2 /p3 /s /vcc /cp2 /cp1 /q3 /q2 /q1 /q0 net-_u1-pad14_ 
+* c:\fossee\esim\library\subcircuitlibrary\74ls95b\74ls95b.cir
+* u11  net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ net-_u1-pad14_ /vcc /q0 ? d_srff
+* u21  net-_u19-pad2_ net-_u18-pad3_ net-_u11-pad3_ net-_u1-pad14_ /vcc /q2 ? d_srff
+* u26  net-_u24-pad2_ net-_u23-pad3_ net-_u11-pad3_ net-_u1-pad14_ /vcc /q3 ? d_srff
+* u6  net-_u3-pad3_ net-_u4-pad3_ net-_u11-pad3_ d_or
+* u3  net-_u12-pad2_ /cp1 net-_u3-pad3_ d_and
+* u4  /s /cp2 net-_u4-pad3_ d_and
+* u8  net-_u10-pad3_ net-_u7-pad3_ net-_u11-pad2_ d_nor
+* u7  /ds net-_u12-pad2_ net-_u7-pad3_ d_and
+* u10  net-_u10-pad1_ /p0 net-_u10-pad3_ d_and
+* u13  net-_u13-pad1_ net-_u12-pad3_ net-_u13-pad3_ d_nor
+* u12  /q0 net-_u12-pad2_ net-_u12-pad3_ d_and
+* u15  net-_u10-pad1_ /p1 net-_u13-pad1_ d_and
+* u18  net-_u18-pad1_ net-_u17-pad3_ net-_u18-pad3_ d_nor
+* u17  /q1 net-_u12-pad2_ net-_u17-pad3_ d_and
+* u20  net-_u10-pad1_ /p2 net-_u18-pad1_ d_and
+* u23  net-_u23-pad1_ net-_u22-pad3_ net-_u23-pad3_ d_nor
+* u22  /q2 net-_u12-pad2_ net-_u22-pad3_ d_and
+* u25  net-_u10-pad1_ /p3 net-_u23-pad1_ d_and
+* u9  net-_u11-pad2_ net-_u11-pad1_ d_inverter
+* u14  net-_u13-pad3_ net-_u14-pad2_ d_inverter
+* u19  net-_u18-pad3_ net-_u19-pad2_ d_inverter
+* u24  net-_u23-pad3_ net-_u24-pad2_ d_inverter
+* u2  /s net-_u12-pad2_ d_inverter
+* u5  net-_u12-pad2_ net-_u10-pad1_ d_inverter
+* u16  net-_u14-pad2_ net-_u13-pad3_ net-_u11-pad3_ net-_u1-pad14_ /vcc /q1 ? d_srff
+a1 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ net-_u1-pad14_ /vcc /q0 ? u11
+a2 net-_u19-pad2_ net-_u18-pad3_ net-_u11-pad3_ net-_u1-pad14_ /vcc /q2 ? u21
+a3 net-_u24-pad2_ net-_u23-pad3_ net-_u11-pad3_ net-_u1-pad14_ /vcc /q3 ? u26
+a4 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u11-pad3_ u6
+a5 [net-_u12-pad2_ /cp1 ] net-_u3-pad3_ u3
+a6 [/s /cp2 ] net-_u4-pad3_ u4
+a7 [net-_u10-pad3_ net-_u7-pad3_ ] net-_u11-pad2_ u8
+a8 [/ds net-_u12-pad2_ ] net-_u7-pad3_ u7
+a9 [net-_u10-pad1_ /p0 ] net-_u10-pad3_ u10
+a10 [net-_u13-pad1_ net-_u12-pad3_ ] net-_u13-pad3_ u13
+a11 [/q0 net-_u12-pad2_ ] net-_u12-pad3_ u12
+a12 [net-_u10-pad1_ /p1 ] net-_u13-pad1_ u15
+a13 [net-_u18-pad1_ net-_u17-pad3_ ] net-_u18-pad3_ u18
+a14 [/q1 net-_u12-pad2_ ] net-_u17-pad3_ u17
+a15 [net-_u10-pad1_ /p2 ] net-_u18-pad1_ u20
+a16 [net-_u23-pad1_ net-_u22-pad3_ ] net-_u23-pad3_ u23
+a17 [/q2 net-_u12-pad2_ ] net-_u22-pad3_ u22
+a18 [net-_u10-pad1_ /p3 ] net-_u23-pad1_ u25
+a19 net-_u11-pad2_ net-_u11-pad1_ u9
+a20 net-_u13-pad3_ net-_u14-pad2_ u14
+a21 net-_u18-pad3_ net-_u19-pad2_ u19
+a22 net-_u23-pad3_ net-_u24-pad2_ u24
+a23 /s net-_u12-pad2_ u2
+a24 net-_u12-pad2_ net-_u10-pad1_ u5
+a25 net-_u14-pad2_ net-_u13-pad3_ net-_u11-pad3_ net-_u1-pad14_ /vcc /q1 ? u16
+* Schematic Name:                             d_srff, NgSpice Name: d_srff
+.model u11 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_srff, NgSpice Name: d_srff
+.model u21 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_srff, NgSpice Name: d_srff
+.model u26 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u6 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u8 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u13 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u18 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u23 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_srff, NgSpice Name: d_srff
+.model u16 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Control Statements
+
+.ends 74LS95B
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74LS95B/74LS95B_Previous_Values.xml b/library/SubcircuitLibrary/74LS95B/74LS95B_Previous_Values.xml
new file mode 100644
index 00000000..661514d9
--- /dev/null
+++ b/library/SubcircuitLibrary/74LS95B/74LS95B_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u11 name="type">d_srff<field1 name="Enter Clk Delay (default=1.0e-9)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter Reset Delay (default=1.0)" /><field4 name="Enter IC (default=0)" /><field5 name="Enter value for SR Load (default=1.0e-12)" /><field6 name="Enter value for Clk Load (default=1.0e-12)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter value for Reset Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /><field10 name="Enter Fall Delay (default=1.0e-9)" /></u11><u16 name="type">d_srff<field11 name="Enter Clk Delay (default=1.0e-9)" /><field12 name="Enter Set Delay (default=1.0e-9)" /><field13 name="Enter Reset Delay (default=1.0)" /><field14 name="Enter IC (default=0)" /><field15 name="Enter value for SR Load (default=1.0e-12)" /><field16 name="Enter value for Clk Load (default=1.0e-12)" /><field17 name="Enter value for Set Load (default=1.0e-12)" /><field18 name="Enter value for Reset Load (default=1.0e-12)" /><field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /></u16><u21 name="type">d_srff<field21 name="Enter Clk Delay (default=1.0e-9)" /><field22 name="Enter Set Delay (default=1.0e-9)" /><field23 name="Enter Reset Delay (default=1.0)" /><field24 name="Enter IC (default=0)" /><field25 name="Enter value for SR Load (default=1.0e-12)" /><field26 name="Enter value for Clk Load (default=1.0e-12)" /><field27 name="Enter value for Set Load (default=1.0e-12)" /><field28 name="Enter value for Reset Load (default=1.0e-12)" /><field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /></u21><u26 name="type">d_srff<field31 name="Enter Clk Delay (default=1.0e-9)" /><field32 name="Enter Set Delay (default=1.0e-9)" /><field33 name="Enter Reset Delay (default=1.0)" /><field34 name="Enter IC (default=0)" /><field35 name="Enter value for SR Load (default=1.0e-12)" /><field36 name="Enter value for Clk Load (default=1.0e-12)" /><field37 name="Enter value for Set Load (default=1.0e-12)" /><field38 name="Enter value for Reset Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /><field40 name="Enter Fall Delay (default=1.0e-9)" /></u26><u6 name="type">d_or<field41 name="Enter Rise Delay (default=1.0e-9)" /><field42 name="Enter Fall Delay (default=1.0e-9)" /><field43 name="Enter Input Load (default=1.0e-12)" /></u6><u3 name="type">d_and<field44 name="Enter Rise Delay (default=1.0e-9)" /><field45 name="Enter Fall Delay (default=1.0e-9)" /><field46 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_and<field47 name="Enter Rise Delay (default=1.0e-9)" /><field48 name="Enter Fall Delay (default=1.0e-9)" /><field49 name="Enter Input Load (default=1.0e-12)" /></u4><u8 name="type">d_nor<field50 name="Enter Rise Delay (default=1.0e-9)" /><field51 name="Enter Fall Delay (default=1.0e-9)" /><field52 name="Enter Input Load (default=1.0e-12)" /></u8><u7 name="type">d_and<field53 name="Enter Rise Delay (default=1.0e-9)" /><field54 name="Enter Fall Delay (default=1.0e-9)" /><field55 name="Enter Input Load (default=1.0e-12)" /></u7><u10 name="type">d_and<field56 name="Enter Rise Delay (default=1.0e-9)" /><field57 name="Enter Fall Delay (default=1.0e-9)" /><field58 name="Enter Input Load (default=1.0e-12)" /></u10><u13 name="type">d_nor<field59 name="Enter Rise Delay (default=1.0e-9)" /><field60 name="Enter Fall Delay (default=1.0e-9)" /><field61 name="Enter Input Load (default=1.0e-12)" /></u13><u12 name="type">d_and<field62 name="Enter Rise Delay (default=1.0e-9)" /><field63 name="Enter Fall Delay (default=1.0e-9)" /><field64 name="Enter Input Load (default=1.0e-12)" /></u12><u15 name="type">d_and<field65 name="Enter Rise Delay (default=1.0e-9)" /><field66 name="Enter Fall Delay (default=1.0e-9)" /><field67 name="Enter Input Load (default=1.0e-12)" /></u15><u18 name="type">d_nor<field68 name="Enter Rise Delay (default=1.0e-9)" /><field69 name="Enter Fall Delay (default=1.0e-9)" /><field70 name="Enter Input Load (default=1.0e-12)" /></u18><u17 name="type">d_and<field71 name="Enter Rise Delay (default=1.0e-9)" /><field72 name="Enter Fall Delay (default=1.0e-9)" /><field73 name="Enter Input Load (default=1.0e-12)" /></u17><u20 name="type">d_and<field74 name="Enter Rise Delay (default=1.0e-9)" /><field75 name="Enter Fall Delay (default=1.0e-9)" /><field76 name="Enter Input Load (default=1.0e-12)" /></u20><u23 name="type">d_nor<field77 name="Enter Rise Delay (default=1.0e-9)" /><field78 name="Enter Fall Delay (default=1.0e-9)" /><field79 name="Enter Input Load (default=1.0e-12)" /></u23><u22 name="type">d_and<field80 name="Enter Rise Delay (default=1.0e-9)" /><field81 name="Enter Fall Delay (default=1.0e-9)" /><field82 name="Enter Input Load (default=1.0e-12)" /></u22><u25 name="type">d_and<field83 name="Enter Rise Delay (default=1.0e-9)" /><field84 name="Enter Fall Delay (default=1.0e-9)" /><field85 name="Enter Input Load (default=1.0e-12)" /></u25><u9 name="type">d_inverter<field86 name="Enter Rise Delay (default=1.0e-9)" /><field87 name="Enter Fall Delay (default=1.0e-9)" /><field88 name="Enter Input Load (default=1.0e-12)" /></u9><u14 name="type">d_inverter<field89 name="Enter Rise Delay (default=1.0e-9)" /><field90 name="Enter Fall Delay (default=1.0e-9)" /><field91 name="Enter Input Load (default=1.0e-12)" /></u14><u19 name="type">d_inverter<field92 name="Enter Rise Delay (default=1.0e-9)" /><field93 name="Enter Fall Delay (default=1.0e-9)" /><field94 name="Enter Input Load (default=1.0e-12)" /></u19><u24 name="type">d_inverter<field95 name="Enter Rise Delay (default=1.0e-9)" /><field96 name="Enter Fall Delay (default=1.0e-9)" /><field97 name="Enter Input Load (default=1.0e-12)" /></u24><u2 name="type">d_inverter<field98 name="Enter Rise Delay (default=1.0e-9)" /><field99 name="Enter Fall Delay (default=1.0e-9)" /><field100 name="Enter Input Load (default=1.0e-12)" /></u2><u5 name="type">d_inverter<field101 name="Enter Rise Delay (default=1.0e-9)" /><field102 name="Enter Fall Delay (default=1.0e-9)" /><field103 name="Enter Input Load (default=1.0e-12)" /></u5><u27 name="type">adc_bridge<field94 name="Enter value for in_low (default=1.0)">0</field94><field95 name="Enter value for in_high (default=2.0)">3.3</field95><field96 name="Enter Rise Delay (default=1.0e-9)" /><field97 name="Enter Fall Delay (default=1.0e-9)" /></u27><u28 name="type">adc_bridge<field98 name="Enter value for in_low (default=1.0)">0</field98><field99 name="Enter value for in_high (default=2.0)">3.3</field99><field100 name="Enter Rise Delay (default=1.0e-9)" /><field101 name="Enter Fall Delay (default=1.0e-9)" /></u28><u29 name="type">adc_bridge<field102 name="Enter value for in_low (default=1.0)">0</field102><field103 name="Enter value for in_high (default=2.0)">3.3</field103><field104 name="Enter Rise Delay (default=1.0e-9)" /><field105 name="Enter Fall Delay (default=1.0e-9)" /></u29><u30 name="type">adc_bridge<field106 name="Enter value for in_low (default=1.0)">0</field106><field107 name="Enter value for in_high (default=2.0)">3.3</field107><field108 name="Enter Rise Delay (default=1.0e-9)" /><field109 name="Enter Fall Delay (default=1.0e-9)" /></u30></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74LS95B/analysis b/library/SubcircuitLibrary/74LS95B/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/74LS95B/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file