74ACT11286 is a high-speed 8-bit comparator

1 files changed, 86 insertions, 0 deletions

diff --git a/library/SubcircuitLibrary/74ACT11286/74ACT11286.sub b/library/SubcircuitLibrary/74ACT11286/74ACT11286.sub
new file mode 100644
index 00000000..bcf12808
--- /dev/null
+++ b/library/SubcircuitLibrary/74ACT11286/74ACT11286.sub
@@ -0,0 +1,86 @@
+* Subcircuit 74ACT11286
+.subckt 74ACT11286 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ 
+* c:\fossee\esim\library\subcircuitlibrary\74act11286\74act11286.cir
+* u17  net-_u1-pad1_ net-_u1-pad2_ net-_u17-pad3_ d_xnor
+* u21  net-_u1-pad3_ net-_u21-pad2_ d_inverter
+* u25  net-_u17-pad3_ net-_u21-pad2_ net-_u25-pad3_ d_xnor
+* u18  net-_u1-pad4_ net-_u1-pad5_ net-_u18-pad3_ d_xnor
+* u22  net-_u1-pad6_ net-_u22-pad2_ d_inverter
+* u26  net-_u18-pad3_ net-_u22-pad2_ net-_u26-pad3_ d_xnor
+* u19  net-_u1-pad7_ net-_u1-pad8_ net-_u19-pad3_ d_xnor
+* u23  net-_u1-pad9_ net-_u23-pad2_ d_inverter
+* u27  net-_u19-pad3_ net-_u23-pad2_ net-_u27-pad3_ d_xnor
+* u29  net-_u25-pad3_ net-_u26-pad3_ net-_u29-pad3_ d_xnor
+* u30  net-_u27-pad3_ net-_u30-pad2_ d_inverter
+* u31  net-_u29-pad3_ net-_u30-pad2_ net-_u24-pad1_ d_xnor
+* u32  net-_u24-pad1_ net-_u32-pad2_ d_inverter
+* u33  net-_u32-pad2_ net-_u28-pad2_ net-_u33-pad3_ d_xnor
+* u35  net-_u33-pad3_ net-_u34-pad2_ net-_u1-pad12_ d_nand
+* u34  net-_u20-pad2_ net-_u34-pad2_ d_inverter
+* u28  net-_u1-pad10_ net-_u28-pad2_ d_inverter
+* u20  net-_u1-pad11_ net-_u20-pad2_ d_inverter
+* u24  net-_u24-pad1_ net-_u20-pad2_ net-_u16-pad1_ d_tristate
+* u16  net-_u16-pad1_ net-_u1-pad10_ d_inverter
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u17-pad3_ u17
+a2 net-_u1-pad3_ net-_u21-pad2_ u21
+a3 [net-_u17-pad3_ net-_u21-pad2_ ] net-_u25-pad3_ u25
+a4 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u18-pad3_ u18
+a5 net-_u1-pad6_ net-_u22-pad2_ u22
+a6 [net-_u18-pad3_ net-_u22-pad2_ ] net-_u26-pad3_ u26
+a7 [net-_u1-pad7_ net-_u1-pad8_ ] net-_u19-pad3_ u19
+a8 net-_u1-pad9_ net-_u23-pad2_ u23
+a9 [net-_u19-pad3_ net-_u23-pad2_ ] net-_u27-pad3_ u27
+a10 [net-_u25-pad3_ net-_u26-pad3_ ] net-_u29-pad3_ u29
+a11 net-_u27-pad3_ net-_u30-pad2_ u30
+a12 [net-_u29-pad3_ net-_u30-pad2_ ] net-_u24-pad1_ u31
+a13 net-_u24-pad1_ net-_u32-pad2_ u32
+a14 [net-_u32-pad2_ net-_u28-pad2_ ] net-_u33-pad3_ u33
+a15 [net-_u33-pad3_ net-_u34-pad2_ ] net-_u1-pad12_ u35
+a16 net-_u20-pad2_ net-_u34-pad2_ u34
+a17 net-_u1-pad10_ net-_u28-pad2_ u28
+a18 net-_u1-pad11_ net-_u20-pad2_ u20
+a19 net-_u24-pad1_ net-_u20-pad2_ net-_u16-pad1_ u24
+a20 net-_u16-pad1_ net-_u1-pad10_ u16
+* Schematic Name:                             d_xnor, NgSpice Name: d_xnor
+.model u17 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_xnor, NgSpice Name: d_xnor
+.model u25 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_xnor, NgSpice Name: d_xnor
+.model u18 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_xnor, NgSpice Name: d_xnor
+.model u26 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_xnor, NgSpice Name: d_xnor
+.model u19 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_xnor, NgSpice Name: d_xnor
+.model u27 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_xnor, NgSpice Name: d_xnor
+.model u29 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_xnor, NgSpice Name: d_xnor
+.model u31 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_xnor, NgSpice Name: d_xnor
+.model u33 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u35 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_tristate, NgSpice Name: d_tristate
+.model u24 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74ACT11286
\ No newline at end of file