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| author | rahulp13 | 2020-02-21 12:36:46 +0530 |
|---|---|---|
| committer | rahulp13 | 2020-02-21 12:36:46 +0530 |
| commit | 47d4daff2ab483c4cdfb82117ef0d25d53832214 (patch) | |
| tree | 55aefefe974f151de76c6a2dbe8df3b4c3393bbe /library/SubcircuitLibrary/74153 | |
| parent | 453c2dab78f81046fcbd42034a86c4e759a0ff68 (diff) | |
| download | eSim-47d4daff2ab483c4cdfb82117ef0d25d53832214.tar.gz eSim-47d4daff2ab483c4cdfb82117ef0d25d53832214.tar.bz2 eSim-47d4daff2ab483c4cdfb82117ef0d25d53832214.zip | |
restructured eSim libraries
Diffstat (limited to 'library/SubcircuitLibrary/74153')
32 files changed, 2701 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/74153/3_and-cache.lib b/library/SubcircuitLibrary/74153/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/74153/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74153/3_and.cir b/library/SubcircuitLibrary/74153/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/74153/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/74153/3_and.cir.out b/library/SubcircuitLibrary/74153/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/74153/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74153/3_and.pro b/library/SubcircuitLibrary/74153/3_and.pro new file mode 100644 index 00000000..2c9ac554 --- /dev/null +++ b/library/SubcircuitLibrary/74153/3_and.pro @@ -0,0 +1,58 @@ +update=03/26/19 18:40:23 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_PSpice +LibName23=eSim_Sources +LibName24=eSim_Subckt +LibName25=eSim_User diff --git a/library/SubcircuitLibrary/74153/3_and.sch b/library/SubcircuitLibrary/74153/3_and.sch new file mode 100644 index 00000000..86be0215 --- /dev/null +++ b/library/SubcircuitLibrary/74153/3_and.sch @@ -0,0 +1,121 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74153/3_and.sub b/library/SubcircuitLibrary/74153/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/74153/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74153/3_and_Previous_Values.xml b/library/SubcircuitLibrary/74153/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/74153/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74153/4_OR-cache.lib b/library/SubcircuitLibrary/74153/4_OR-cache.lib new file mode 100644 index 00000000..155f5e60 --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_OR-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74153/4_OR.cir b/library/SubcircuitLibrary/74153/4_OR.cir new file mode 100644 index 00000000..b338b7b5 --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_OR.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/74153/4_OR.cir.out b/library/SubcircuitLibrary/74153/4_OR.cir.out new file mode 100644 index 00000000..adb6b01b --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_OR.cir.out @@ -0,0 +1,24 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74153/4_OR.pro b/library/SubcircuitLibrary/74153/4_OR.pro new file mode 100644 index 00000000..2c258cec --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_OR.pro @@ -0,0 +1,45 @@ +update=03/28/19 22:43:48 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_PSpice +LibName10=eSim_Sources +LibName11=eSim_Subckt +LibName12=eSim_User diff --git a/library/SubcircuitLibrary/74153/4_OR.sch b/library/SubcircuitLibrary/74153/4_OR.sch new file mode 100644 index 00000000..11896865 --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_OR.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5C9D00E1 +P 4300 2950 +F 0 "U2" H 4300 2950 60 0000 C CNN +F 1 "d_or" H 4300 3050 60 0000 C CNN +F 2 "" H 4300 2950 60 0000 C CNN +F 3 "" H 4300 2950 60 0000 C CNN + 1 4300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5C9D011F +P 4300 3350 +F 0 "U3" H 4300 3350 60 0000 C CNN +F 1 "d_or" H 4300 3450 60 0000 C CNN +F 2 "" H 4300 3350 60 0000 C CNN +F 3 "" H 4300 3350 60 0000 C CNN + 1 4300 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 5C9D0141 +P 5250 3150 +F 0 "U4" H 5250 3150 60 0000 C CNN +F 1 "d_or" H 5250 3250 60 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 3050 4800 2900 +Wire Wire Line + 4800 2900 4750 2900 +Wire Wire Line + 4800 3150 4800 3300 +Wire Wire Line + 4800 3300 4750 3300 +Wire Wire Line + 3350 2850 3850 2850 +Wire Wire Line + 3850 2950 3600 2950 +Wire Wire Line + 3850 3250 3350 3250 +Wire Wire Line + 3600 2950 3600 3000 +Wire Wire Line + 3600 3000 3350 3000 +Wire Wire Line + 3850 3350 3850 3400 +Wire Wire Line + 3850 3400 3350 3400 +Wire Wire Line + 5700 3100 6200 3100 +$Comp +L PORT U1 +U 1 1 5C9D01F4 +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 1 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9D022F +P 3100 3000 +F 0 "U1" H 3150 3100 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0000 C CNN +F 3 "" H 3100 3000 60 0000 C CNN + 2 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9D0271 +P 3100 3250 +F 0 "U1" H 3150 3350 30 0000 C CNN +F 1 "PORT" H 3100 3250 30 0000 C CNN +F 2 "" H 3100 3250 60 0000 C CNN +F 3 "" H 3100 3250 60 0000 C CNN + 3 3100 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9D0299 +P 3100 3400 +F 0 "U1" H 3150 3500 30 0000 C CNN +F 1 "PORT" H 3100 3400 30 0000 C CNN +F 2 "" H 3100 3400 60 0000 C CNN +F 3 "" H 3100 3400 60 0000 C CNN + 4 3100 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9D02C2 +P 6450 3100 +F 0 "U1" H 6500 3200 30 0000 C CNN +F 1 "PORT" H 6450 3100 30 0000 C CNN +F 2 "" H 6450 3100 60 0000 C CNN +F 3 "" H 6450 3100 60 0000 C CNN + 5 6450 3100 + -1 0 0 1 +$EndComp +Text Notes 3450 2850 0 60 ~ 12 +in1 +Text Notes 3450 3000 0 60 ~ 12 +in2 +Text Notes 3450 3250 0 60 ~ 12 +in3 +Text Notes 3450 3400 0 60 ~ 12 +in4 +Text Notes 5800 3100 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74153/4_OR.sub b/library/SubcircuitLibrary/74153/4_OR.sub new file mode 100644 index 00000000..d1fd3a24 --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_OR.sub @@ -0,0 +1,18 @@ +* Subcircuit 4_OR +.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_OR
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74153/4_OR_Previous_Values.xml b/library/SubcircuitLibrary/74153/4_OR_Previous_Values.xml new file mode 100644 index 00000000..23698d37 --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_OR_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74153/4_and-cache.lib b/library/SubcircuitLibrary/74153/4_and-cache.lib new file mode 100644 index 00000000..ac396288 --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74153/4_and.cir b/library/SubcircuitLibrary/74153/4_and.cir new file mode 100644 index 00000000..50d490fa --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 19:01:09 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/74153/4_and.cir.out b/library/SubcircuitLibrary/74153/4_and.cir.out new file mode 100644 index 00000000..f40e5bc6 --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74153/4_and.pro b/library/SubcircuitLibrary/74153/4_and.pro new file mode 100644 index 00000000..6eb77fff --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_and.pro @@ -0,0 +1,57 @@ +update=03/26/19 18:58:33 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=texas +LibName2=intel +LibName3=audio +LibName4=interface +LibName5=digital-audio +LibName6=philips +LibName7=display +LibName8=cypress +LibName9=siliconi +LibName10=opto +LibName11=atmel +LibName12=contrib +LibName13=valves +LibName14=eSim_Analog +LibName15=eSim_Devices +LibName16=eSim_Digital +LibName17=eSim_Hybrid +LibName18=eSim_Miscellaneous +LibName19=eSim_Plot +LibName20=eSim_Power +LibName21=eSim_PSpice +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/library/SubcircuitLibrary/74153/4_and.sch b/library/SubcircuitLibrary/74153/4_and.sch new file mode 100644 index 00000000..883458e1 --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_and.sch @@ -0,0 +1,139 @@ +EESchema Schematic File Version 2 +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74153/4_and.sub b/library/SubcircuitLibrary/74153/4_and.sub new file mode 100644 index 00000000..8663f37e --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74153/4_and_Previous_Values.xml b/library/SubcircuitLibrary/74153/4_and_Previous_Values.xml new file mode 100644 index 00000000..f2ba0130 --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74153/74153-cache.lib b/library/SubcircuitLibrary/74153/74153-cache.lib new file mode 100644 index 00000000..1e85854e --- /dev/null +++ b/library/SubcircuitLibrary/74153/74153-cache.lib @@ -0,0 +1,98 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 3900 3050 60 H V C CNN +F1 "4_OR" 3900 3250 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 2950 3150 650 226 -226 0 1 0 N 3550 3400 3550 2900 +A 3677 3284 444 -599 -176 0 1 0 N 3900 2900 4100 3150 +A 3720 3051 393 627 146 0 1 0 N 3900 3400 4100 3150 +P 2 0 1 0 3550 2900 3900 2900 N +P 2 0 1 0 3550 3400 3900 3400 N +X in1 1 3400 3300 200 R 50 50 1 1 I +X in2 2 3400 3200 200 R 50 50 1 1 I +X in3 3 3400 3100 200 R 50 50 1 1 I +X in4 4 3400 3000 200 R 50 50 1 1 I +X out 5 4300 3150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 1500 1050 60 H V C CNN +F1 "4_and" 1550 1200 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 1550 1100 206 760 -760 0 1 0 N 1600 1300 1600 900 +P 2 0 1 0 1250 1300 1600 1300 N +P 4 0 1 0 1250 1300 1250 900 1500 900 1600 900 N +X in1 1 1050 1250 200 R 50 50 1 1 I +X in2 2 1050 1150 200 R 50 50 1 1 I +X in3 3 1050 1050 200 R 50 50 1 1 I +X in4 4 1050 950 200 R 50 50 1 1 I +X out 5 1950 1100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74153/74153.cir b/library/SubcircuitLibrary/74153/74153.cir new file mode 100644 index 00000000..b20e6858 --- /dev/null +++ b/library/SubcircuitLibrary/74153/74153.cir @@ -0,0 +1,25 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\74153\74153.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 23:33:11 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad12_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad11_ Net-_U3-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT +U35 Net-_U1-Pad5_ Net-_U35-Pad2_ d_inverter +U34 Net-_U1-Pad10_ Net-_U34-Pad2_ d_inverter +X8 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad1_ Net-_U35-Pad2_ Net-_X2-Pad1_ 4_and +X9 Net-_U1-Pad12_ Net-_U3-Pad2_ Net-_U1-Pad2_ Net-_U35-Pad2_ Net-_X2-Pad2_ 4_and +X4 Net-_U2-Pad2_ Net-_U1-Pad11_ Net-_U1-Pad3_ Net-_U35-Pad2_ Net-_X2-Pad3_ 4_and +X10 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad4_ Net-_U35-Pad2_ Net-_X10-Pad5_ 4_and +X5 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad6_ Net-_U34-Pad2_ Net-_X1-Pad1_ 4_and +X6 Net-_U1-Pad12_ Net-_U3-Pad2_ Net-_U1-Pad7_ Net-_U34-Pad2_ Net-_X1-Pad2_ 4_and +X3 Net-_U2-Pad2_ Net-_U1-Pad11_ Net-_U1-Pad8_ Net-_U34-Pad2_ Net-_X1-Pad3_ 4_and +X7 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad9_ Net-_U34-Pad2_ Net-_X1-Pad4_ 4_and +X1 Net-_X1-Pad1_ Net-_X1-Pad2_ Net-_X1-Pad3_ Net-_X1-Pad4_ Net-_U1-Pad14_ 4_OR +X2 Net-_X2-Pad1_ Net-_X2-Pad2_ Net-_X2-Pad3_ Net-_X10-Pad5_ Net-_U1-Pad13_ 4_OR + +.end diff --git a/library/SubcircuitLibrary/74153/74153.cir.out b/library/SubcircuitLibrary/74153/74153.cir.out new file mode 100644 index 00000000..c95e5ad9 --- /dev/null +++ b/library/SubcircuitLibrary/74153/74153.cir.out @@ -0,0 +1,40 @@ +* c:\users\malli\esim\src\subcircuitlibrary\74153\74153.cir + +.include 4_and.sub +.include 4_OR.sub +* u2 net-_u1-pad12_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad11_ net-_u3-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +* u35 net-_u1-pad5_ net-_u35-pad2_ d_inverter +* u34 net-_u1-pad10_ net-_u34-pad2_ d_inverter +x8 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad1_ net-_u35-pad2_ net-_x2-pad1_ 4_and +x9 net-_u1-pad12_ net-_u3-pad2_ net-_u1-pad2_ net-_u35-pad2_ net-_x2-pad2_ 4_and +x4 net-_u2-pad2_ net-_u1-pad11_ net-_u1-pad3_ net-_u35-pad2_ net-_x2-pad3_ 4_and +x10 net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad4_ net-_u35-pad2_ net-_x10-pad5_ 4_and +x5 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad6_ net-_u34-pad2_ net-_x1-pad1_ 4_and +x6 net-_u1-pad12_ net-_u3-pad2_ net-_u1-pad7_ net-_u34-pad2_ net-_x1-pad2_ 4_and +x3 net-_u2-pad2_ net-_u1-pad11_ net-_u1-pad8_ net-_u34-pad2_ net-_x1-pad3_ 4_and +x7 net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad9_ net-_u34-pad2_ net-_x1-pad4_ 4_and +x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_u1-pad14_ 4_OR +x2 net-_x2-pad1_ net-_x2-pad2_ net-_x2-pad3_ net-_x10-pad5_ net-_u1-pad13_ 4_OR +a1 net-_u1-pad12_ net-_u2-pad2_ u2 +a2 net-_u1-pad11_ net-_u3-pad2_ u3 +a3 net-_u1-pad5_ net-_u35-pad2_ u35 +a4 net-_u1-pad10_ net-_u34-pad2_ u34 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74153/74153.pro b/library/SubcircuitLibrary/74153/74153.pro new file mode 100644 index 00000000..ed8b8bf2 --- /dev/null +++ b/library/SubcircuitLibrary/74153/74153.pro @@ -0,0 +1,59 @@ +update=03/28/19 23:27:36 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=texas +LibName4=intel +LibName5=audio +LibName6=interface +LibName7=digital-audio +LibName8=philips +LibName9=display +LibName10=cypress +LibName11=siliconi +LibName12=opto +LibName13=atmel +LibName14=contrib +LibName15=valves +LibName16=eSim_Analog +LibName17=eSim_Devices +LibName18=eSim_Digital +LibName19=eSim_Hybrid +LibName20=eSim_Miscellaneous +LibName21=eSim_Plot +LibName22=eSim_Power +LibName23=eSim_PSpice +LibName24=eSim_Sources +LibName25=eSim_User +LibName26=eSim_Subckt diff --git a/library/SubcircuitLibrary/74153/74153.sch b/library/SubcircuitLibrary/74153/74153.sch new file mode 100644 index 00000000..e0bcf950 --- /dev/null +++ b/library/SubcircuitLibrary/74153/74153.sch @@ -0,0 +1,568 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:74153-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U2 +U 1 1 5C9378F6 +P 2650 1350 +F 0 "U2" H 2650 1250 60 0000 C CNN +F 1 "d_inverter" H 2650 1500 60 0000 C CNN +F 2 "" H 2700 1300 60 0000 C CNN +F 3 "" H 2700 1300 60 0000 C CNN + 1 2650 1350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 5C93798D +P 2700 950 +F 0 "U3" H 2700 850 60 0000 C CNN +F 1 "d_inverter" H 2700 1100 60 0000 C CNN +F 2 "" H 2750 900 60 0000 C CNN +F 3 "" H 2750 900 60 0000 C CNN + 1 2700 950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C93A0F9 +P 1350 2050 +F 0 "U1" H 1400 2150 30 0000 C CNN +F 1 "PORT" H 1350 2050 30 0000 C CNN +F 2 "" H 1350 2050 60 0000 C CNN +F 3 "" H 1350 2050 60 0000 C CNN + 1 1350 2050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C93A174 +P 1350 4700 +F 0 "U1" H 1400 4800 30 0000 C CNN +F 1 "PORT" H 1350 4700 30 0000 C CNN +F 2 "" H 1350 4700 60 0000 C CNN +F 3 "" H 1350 4700 60 0000 C CNN + 6 1350 4700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C93AA3C +P 1350 2600 +F 0 "U1" H 1400 2700 30 0000 C CNN +F 1 "PORT" H 1350 2600 30 0000 C CNN +F 2 "" H 1350 2600 60 0000 C CNN +F 3 "" H 1350 2600 60 0000 C CNN + 2 1350 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C93AACB +P 1350 3200 +F 0 "U1" H 1400 3300 30 0000 C CNN +F 1 "PORT" H 1350 3200 30 0000 C CNN +F 2 "" H 1350 3200 60 0000 C CNN +F 3 "" H 1350 3200 60 0000 C CNN + 3 1350 3200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C93AB5F +P 1350 3700 +F 0 "U1" H 1400 3800 30 0000 C CNN +F 1 "PORT" H 1350 3700 30 0000 C CNN +F 2 "" H 1350 3700 60 0000 C CNN +F 3 "" H 1350 3700 60 0000 C CNN + 4 1350 3700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5C93AD97 +P 1350 5250 +F 0 "U1" H 1400 5350 30 0000 C CNN +F 1 "PORT" H 1350 5250 30 0000 C CNN +F 2 "" H 1350 5250 60 0000 C CNN +F 3 "" H 1350 5250 60 0000 C CNN + 7 1350 5250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5C93ADFC +P 1350 5850 +F 0 "U1" H 1400 5950 30 0000 C CNN +F 1 "PORT" H 1350 5850 30 0000 C CNN +F 2 "" H 1350 5850 60 0000 C CNN +F 3 "" H 1350 5850 60 0000 C CNN + 8 1350 5850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5C93AE63 +P 1350 6350 +F 0 "U1" H 1400 6450 30 0000 C CNN +F 1 "PORT" H 1350 6350 30 0000 C CNN +F 2 "" H 1350 6350 60 0000 C CNN +F 3 "" H 1350 6350 60 0000 C CNN + 9 1350 6350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C93AECA +P 1350 3950 +F 0 "U1" H 1400 4050 30 0000 C CNN +F 1 "PORT" H 1350 3950 30 0000 C CNN +F 2 "" H 1350 3950 60 0000 C CNN +F 3 "" H 1350 3950 60 0000 C CNN + 5 1350 3950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5C93AF79 +P 1350 6600 +F 0 "U1" H 1400 6700 30 0000 C CNN +F 1 "PORT" H 1350 6600 30 0000 C CNN +F 2 "" H 1350 6600 60 0000 C CNN +F 3 "" H 1350 6600 60 0000 C CNN + 10 1350 6600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5C93B10A +P 1550 950 +F 0 "U1" H 1600 1050 30 0000 C CNN +F 1 "PORT" H 1550 950 30 0000 C CNN +F 2 "" H 1550 950 60 0000 C CNN +F 3 "" H 1550 950 60 0000 C CNN + 11 1550 950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5C93B179 +P 1550 1350 +F 0 "U1" H 1600 1450 30 0000 C CNN +F 1 "PORT" H 1550 1350 30 0000 C CNN +F 2 "" H 1550 1350 60 0000 C CNN +F 3 "" H 1550 1350 60 0000 C CNN + 12 1550 1350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 5C93B567 +P 7850 2600 +F 0 "U1" H 7900 2700 30 0000 C CNN +F 1 "PORT" H 7850 2600 30 0000 C CNN +F 2 "" H 7850 2600 60 0000 C CNN +F 3 "" H 7850 2600 60 0000 C CNN + 13 7850 2600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5C93B5DA +P 7900 5250 +F 0 "U1" H 7950 5350 30 0000 C CNN +F 1 "PORT" H 7900 5250 30 0000 C CNN +F 2 "" H 7900 5250 60 0000 C CNN +F 3 "" H 7900 5250 60 0000 C CNN + 14 7900 5250 + -1 0 0 1 +$EndComp +$Comp +L d_inverter U35 +U 1 1 5C95CBCC +P 2700 3950 +F 0 "U35" H 2700 3850 60 0000 C CNN +F 1 "d_inverter" H 2700 4100 60 0000 C CNN +F 2 "" H 2750 3900 60 0000 C CNN +F 3 "" H 2750 3900 60 0000 C CNN + 1 2700 3950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U34 +U 1 1 5C95CC99 +P 2650 6600 +F 0 "U34" H 2650 6500 60 0000 C CNN +F 1 "d_inverter" H 2650 6750 60 0000 C CNN +F 2 "" H 2700 6550 60 0000 C CNN +F 3 "" H 2700 6550 60 0000 C CNN + 1 2650 6600 + 1 0 0 -1 +$EndComp +Text Notes 1750 2050 0 60 ~ 12 +A0 +Text Notes 1800 2600 0 60 ~ 12 +A1 +Text Notes 1800 3200 0 60 ~ 12 +A2 +Text Notes 1750 3700 0 60 ~ 12 +A3\n +Text Notes 1750 3950 0 60 ~ 12 +EnA\n +Text Notes 1800 4700 0 60 ~ 12 +B0\n +Text Notes 1800 5250 0 60 ~ 12 +B1 +Text Notes 1800 5850 0 60 ~ 12 +B2 +Text Notes 1750 6350 0 60 ~ 12 +B3 +Text Notes 1800 6600 0 60 ~ 12 +EnB +Text Notes 2000 950 0 60 ~ 12 +S1\n +Text Notes 2000 1350 0 60 ~ 12 +S0 +Text Notes 7350 2600 0 60 ~ 12 +YA +Text Notes 7400 5250 0 60 ~ 12 +YB +$Comp +L 4_and X8 +U 1 1 5C9D0C22 +P 2750 3050 +F 0 "X8" H 4250 4100 60 0000 C CNN +F 1 "4_and" H 4300 4250 60 0000 C CNN +F 2 "" H 2750 3050 60 0000 C CNN +F 3 "" H 2750 3050 60 0000 C CNN + 1 2750 3050 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X9 +U 1 1 5C9D0CA2 +P 2750 3600 +F 0 "X9" H 4250 4650 60 0000 C CNN +F 1 "4_and" H 4300 4800 60 0000 C CNN +F 2 "" H 2750 3600 60 0000 C CNN +F 3 "" H 2750 3600 60 0000 C CNN + 1 2750 3600 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X4 +U 1 1 5C9D0D16 +P 2700 4200 +F 0 "X4" H 4200 5250 60 0000 C CNN +F 1 "4_and" H 4250 5400 60 0000 C CNN +F 2 "" H 2700 4200 60 0000 C CNN +F 3 "" H 2700 4200 60 0000 C CNN + 1 2700 4200 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X10 +U 1 1 5C9D0D93 +P 2750 4700 +F 0 "X10" H 4250 5750 60 0000 C CNN +F 1 "4_and" H 4300 5900 60 0000 C CNN +F 2 "" H 2750 4700 60 0000 C CNN +F 3 "" H 2750 4700 60 0000 C CNN + 1 2750 4700 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X5 +U 1 1 5C9D182A +P 2700 5700 +F 0 "X5" H 4200 6750 60 0000 C CNN +F 1 "4_and" H 4250 6900 60 0000 C CNN +F 2 "" H 2700 5700 60 0000 C CNN +F 3 "" H 2700 5700 60 0000 C CNN + 1 2700 5700 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X6 +U 1 1 5C9D1830 +P 2700 6250 +F 0 "X6" H 4200 7300 60 0000 C CNN +F 1 "4_and" H 4250 7450 60 0000 C CNN +F 2 "" H 2700 6250 60 0000 C CNN +F 3 "" H 2700 6250 60 0000 C CNN + 1 2700 6250 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X3 +U 1 1 5C9D1836 +P 2650 6850 +F 0 "X3" H 4150 7900 60 0000 C CNN +F 1 "4_and" H 4200 8050 60 0000 C CNN +F 2 "" H 2650 6850 60 0000 C CNN +F 3 "" H 2650 6850 60 0000 C CNN + 1 2650 6850 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X7 +U 1 1 5C9D183C +P 2700 7350 +F 0 "X7" H 4200 8400 60 0000 C CNN +F 1 "4_and" H 4250 8550 60 0000 C CNN +F 2 "" H 2700 7350 60 0000 C CNN +F 3 "" H 2700 7350 60 0000 C CNN + 1 2700 7350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3100 1800 3800 1800 +Wire Wire Line + 3100 1350 3100 5600 +Wire Wire Line + 3200 1900 3800 1900 +Wire Wire Line + 3200 950 3200 5100 +Wire Wire Line + 2950 1350 3100 1350 +Connection ~ 3100 1800 +Wire Wire Line + 3000 950 3200 950 +Connection ~ 3200 1900 +Wire Wire Line + 1800 950 2400 950 +Wire Wire Line + 1800 1350 2350 1350 +Wire Wire Line + 2200 950 2200 6200 +Connection ~ 2200 950 +Wire Wire Line + 2300 1350 2300 6100 +Wire Wire Line + 3300 2100 3800 2100 +Wire Wire Line + 3300 2100 3300 3800 +Wire Wire Line + 3300 2700 3800 2700 +Wire Wire Line + 3300 3300 3750 3300 +Connection ~ 3300 2700 +Wire Wire Line + 3000 3800 3800 3800 +Connection ~ 3300 3300 +Wire Wire Line + 1600 3700 3800 3700 +Wire Wire Line + 1600 3200 3750 3200 +Wire Wire Line + 3400 2600 1600 2600 +Wire Wire Line + 1600 2050 3800 2050 +Wire Wire Line + 3000 3800 3000 3950 +Wire Wire Line + 1600 3950 2400 3950 +Connection ~ 3300 3800 +Wire Wire Line + 3100 4450 3750 4450 +Wire Wire Line + 3200 4550 3750 4550 +Wire Wire Line + 3300 4800 3750 4800 +Wire Wire Line + 3300 4800 3300 6450 +Wire Wire Line + 3300 5350 3750 5350 +Wire Wire Line + 3300 5950 3700 5950 +Connection ~ 3300 5350 +Wire Wire Line + 3200 6450 3750 6450 +Connection ~ 3300 5950 +Wire Wire Line + 3350 6350 1600 6350 +Wire Wire Line + 1600 5850 3700 5850 +Wire Wire Line + 1600 5250 3750 5250 +Wire Wire Line + 3350 4700 1600 4700 +Wire Wire Line + 3200 6600 3200 6450 +Wire Wire Line + 2950 6600 3200 6600 +Wire Wire Line + 1600 6600 2350 6600 +Connection ~ 3300 6450 +Connection ~ 2300 1350 +Connection ~ 3100 4450 +Connection ~ 3200 4550 +Wire Wire Line + 6550 2600 7600 2600 +Wire Wire Line + 6450 5250 7650 5250 +Connection ~ 2200 3450 +Wire Wire Line + 3200 5100 3750 5100 +Wire Wire Line + 2300 5000 3750 5000 +Connection ~ 2300 5000 +Wire Wire Line + 3100 5600 3700 5600 +Wire Wire Line + 2200 5700 3700 5700 +Wire Wire Line + 2200 6200 3750 6200 +Connection ~ 2200 5700 +Wire Wire Line + 2300 6100 3750 6100 +Wire Wire Line + 3200 2450 3800 2450 +Connection ~ 3200 2450 +Wire Wire Line + 2300 2350 3800 2350 +Connection ~ 2300 2350 +Wire Wire Line + 2200 3050 3750 3050 +Connection ~ 2200 3050 +Wire Wire Line + 3100 2950 3750 2950 +Connection ~ 3100 2950 +Wire Wire Line + 2300 3450 3800 3450 +Wire Wire Line + 2300 3450 2300 3400 +Connection ~ 2300 3400 +Wire Wire Line + 2200 3550 3800 3550 +Connection ~ 2200 3550 +Wire Wire Line + 3800 2050 3800 2000 +Wire Wire Line + 3400 2600 3400 2550 +Wire Wire Line + 3400 2550 3800 2550 +Wire Wire Line + 3800 2700 3800 2650 +Wire Wire Line + 3750 3200 3750 3150 +Wire Wire Line + 3750 3300 3750 3250 +Wire Wire Line + 3800 3700 3800 3650 +Wire Wire Line + 3800 3800 3800 3750 +Wire Wire Line + 3350 4700 3350 4650 +Wire Wire Line + 3350 4650 3750 4650 +Wire Wire Line + 3750 4800 3750 4750 +Wire Wire Line + 3750 5250 3750 5200 +Wire Wire Line + 3750 5350 3750 5300 +Wire Wire Line + 3700 5850 3700 5800 +Wire Wire Line + 3700 5950 3700 5900 +Wire Wire Line + 3350 6350 3350 6300 +Wire Wire Line + 3350 6300 3750 6300 +Wire Wire Line + 3750 6450 3750 6400 +$Comp +L 4_OR X1 +U 1 1 5C9D22F7 +P 2150 8400 +F 0 "X1" H 6050 11450 60 0000 C CNN +F 1 "4_OR" H 6050 11650 60 0000 C CNN +F 2 "" H 2150 8400 60 0000 C CNN +F 3 "" H 2150 8400 60 0000 C CNN + 1 2150 8400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5550 5100 5550 4600 +Wire Wire Line + 5550 4600 4650 4600 +Wire Wire Line + 5550 5200 4650 5200 +Wire Wire Line + 4650 5200 4650 5150 +Wire Wire Line + 4600 5750 4600 5300 +Wire Wire Line + 4600 5300 5550 5300 +Wire Wire Line + 4650 6250 4650 5400 +Wire Wire Line + 4650 5400 5550 5400 +$Comp +L 4_OR X2 +U 1 1 5C9D28DE +P 2250 5750 +F 0 "X2" H 6150 8800 60 0000 C CNN +F 1 "4_OR" H 6150 9000 60 0000 C CNN +F 2 "" H 2250 5750 60 0000 C CNN +F 3 "" H 2250 5750 60 0000 C CNN + 1 2250 5750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4700 1950 5650 1950 +Wire Wire Line + 5650 1950 5650 2450 +Wire Wire Line + 5650 2550 4700 2550 +Wire Wire Line + 4700 2550 4700 2500 +Wire Wire Line + 4650 3100 4650 2650 +Wire Wire Line + 4650 2650 5650 2650 +Wire Wire Line + 4700 3600 4700 2750 +Wire Wire Line + 4700 2750 5650 2750 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74153/74153.sub b/library/SubcircuitLibrary/74153/74153.sub new file mode 100644 index 00000000..6e00261f --- /dev/null +++ b/library/SubcircuitLibrary/74153/74153.sub @@ -0,0 +1,34 @@ +* Subcircuit 74153 +.subckt 74153 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\users\malli\esim\src\subcircuitlibrary\74153\74153.cir +.include 4_and.sub +.include 4_OR.sub +* u2 net-_u1-pad12_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad11_ net-_u3-pad2_ d_inverter +* u35 net-_u1-pad5_ net-_u35-pad2_ d_inverter +* u34 net-_u1-pad10_ net-_u34-pad2_ d_inverter +x8 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad1_ net-_u35-pad2_ net-_x2-pad1_ 4_and +x9 net-_u1-pad12_ net-_u3-pad2_ net-_u1-pad2_ net-_u35-pad2_ net-_x2-pad2_ 4_and +x4 net-_u2-pad2_ net-_u1-pad11_ net-_u1-pad3_ net-_u35-pad2_ net-_x2-pad3_ 4_and +x10 net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad4_ net-_u35-pad2_ net-_x10-pad5_ 4_and +x5 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad6_ net-_u34-pad2_ net-_x1-pad1_ 4_and +x6 net-_u1-pad12_ net-_u3-pad2_ net-_u1-pad7_ net-_u34-pad2_ net-_x1-pad2_ 4_and +x3 net-_u2-pad2_ net-_u1-pad11_ net-_u1-pad8_ net-_u34-pad2_ net-_x1-pad3_ 4_and +x7 net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad9_ net-_u34-pad2_ net-_x1-pad4_ 4_and +x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_u1-pad14_ 4_OR +x2 net-_x2-pad1_ net-_x2-pad2_ net-_x2-pad3_ net-_x10-pad5_ net-_u1-pad13_ 4_OR +a1 net-_u1-pad12_ net-_u2-pad2_ u2 +a2 net-_u1-pad11_ net-_u3-pad2_ u3 +a3 net-_u1-pad5_ net-_u35-pad2_ u35 +a4 net-_u1-pad10_ net-_u34-pad2_ u34 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 74153
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74153/74153_Previous_Values.xml b/library/SubcircuitLibrary/74153/74153_Previous_Values.xml new file mode 100644 index 00000000..ea70e6f3 --- /dev/null +++ b/library/SubcircuitLibrary/74153/74153_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u14 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u14><u25 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u25><u5 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u5><u20 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u20><u7 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u7><u21 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u21><u18 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u18><u24 name="type">d_and<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u24><u28 name="type">d_or<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u28><u29 name="type">d_or<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u29><u32 name="type">d_or<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u32><u2 name="type">d_inverter<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u3><u15 name="type">d_and<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u15><u6 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u6><u8 name="type">d_and<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u8><u4 name="type">d_and<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u4><u16 name="type">d_and<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u16><u27 name="type">d_and<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u27><u10 name="type">d_and<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u10><u22 name="type">d_and<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u22><u12 name="type">d_and<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /></u12><u23 name="type">d_and<field67 name="Enter Fall Delay (default=1.0e-9)" /><field68 name="Enter Input Load (default=1.0e-12)" /><field69 name="Enter Rise Delay (default=1.0e-9)" /></u23><u19 name="type">d_and<field70 name="Enter Fall Delay (default=1.0e-9)" /><field71 name="Enter Input Load (default=1.0e-12)" /><field72 name="Enter Rise Delay (default=1.0e-9)" /></u19><u26 name="type">d_and<field73 name="Enter Fall Delay (default=1.0e-9)" /><field74 name="Enter Input Load (default=1.0e-12)" /><field75 name="Enter Rise Delay (default=1.0e-9)" /></u26><u30 name="type">d_or<field76 name="Enter Fall Delay (default=1.0e-9)" /><field77 name="Enter Input Load (default=1.0e-12)" /><field78 name="Enter Rise Delay (default=1.0e-9)" /></u30><u31 name="type">d_or<field79 name="Enter Fall Delay (default=1.0e-9)" /><field80 name="Enter Input Load (default=1.0e-12)" /><field81 name="Enter Rise Delay (default=1.0e-9)" /></u31><u33 name="type">d_or<field82 name="Enter Fall Delay (default=1.0e-9)" /><field83 name="Enter Input Load (default=1.0e-12)" /><field84 name="Enter Rise Delay (default=1.0e-9)" /></u33><u17 name="type">d_and<field85 name="Enter Fall Delay (default=1.0e-9)" /><field86 name="Enter Input Load (default=1.0e-12)" /><field87 name="Enter Rise Delay (default=1.0e-9)" /></u17><u11 name="type">d_and<field88 name="Enter Fall Delay (default=1.0e-9)" /><field89 name="Enter Input Load (default=1.0e-12)" /><field90 name="Enter Rise Delay (default=1.0e-9)" /></u11><u13 name="type">d_and<field91 name="Enter Fall Delay (default=1.0e-9)" /><field92 name="Enter Input Load (default=1.0e-12)" /><field93 name="Enter Rise Delay (default=1.0e-9)" /></u13><u9 name="type">d_and<field94 name="Enter Fall Delay (default=1.0e-9)" /><field95 name="Enter Input Load (default=1.0e-12)" /><field96 name="Enter Rise Delay (default=1.0e-9)" /></u9><u35 name="type">d_inverter<field97 name="Enter Fall Delay (default=1.0e-9)" /><field98 name="Enter Input Load (default=1.0e-12)" /><field99 name="Enter Rise Delay (default=1.0e-9)" /></u35><u34 name="type">d_inverter<field100 name="Enter Fall Delay (default=1.0e-9)" /><field101 name="Enter Input Load (default=1.0e-12)" /><field102 name="Enter Rise Delay (default=1.0e-9)" /></u34></model><devicemodel /><subcircuit><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR</field></x2><x8><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x8><x9><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x9><x10><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x10><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR</field></x1><x6><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x6><x7><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x7><x4><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x4><x5><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74153/Dual4to1MUX-cache.lib b/library/SubcircuitLibrary/74153/Dual4to1MUX-cache.lib new file mode 100644 index 00000000..10496d63 --- /dev/null +++ b/library/SubcircuitLibrary/74153/Dual4to1MUX-cache.lib @@ -0,0 +1,94 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74153/Dual4to1MUX.cir b/library/SubcircuitLibrary/74153/Dual4to1MUX.cir new file mode 100644 index 00000000..583c4a00 --- /dev/null +++ b/library/SubcircuitLibrary/74153/Dual4to1MUX.cir @@ -0,0 +1,45 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\74153\Dual4to1MUX.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/23/19 11:18:42 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U14 Net-_U1-Pad12_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_and +U25 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U25-Pad3_ d_and +U5 Net-_U10-Pad1_ Net-_U1-Pad11_ Net-_U20-Pad1_ d_and +U20 Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U20-Pad3_ d_and +U7 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U21-Pad1_ d_and +U21 Net-_U21-Pad1_ Net-_U21-Pad2_ Net-_U21-Pad3_ d_and +U18 Net-_U10-Pad1_ Net-_U14-Pad2_ Net-_U18-Pad3_ d_and +U24 Net-_U18-Pad3_ Net-_U24-Pad2_ Net-_U24-Pad3_ d_and +U28 Net-_U24-Pad3_ Net-_U25-Pad3_ Net-_U28-Pad3_ d_or +U29 Net-_U20-Pad3_ Net-_U21-Pad3_ Net-_U29-Pad3_ d_or +U32 Net-_U28-Pad3_ Net-_U29-Pad3_ Net-_U1-Pad13_ d_or +U2 Net-_U1-Pad12_ Net-_U10-Pad1_ d_inverter +U3 Net-_U1-Pad11_ Net-_U14-Pad2_ d_inverter +U15 Net-_U1-Pad2_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_and +U6 Net-_U1-Pad3_ Net-_U15-Pad2_ Net-_U20-Pad2_ d_and +U8 Net-_U1-Pad4_ Net-_U15-Pad2_ Net-_U21-Pad2_ d_and +U4 Net-_U1-Pad1_ Net-_U15-Pad2_ Net-_U24-Pad2_ d_and +U16 Net-_U1-Pad12_ Net-_U14-Pad2_ Net-_U16-Pad3_ d_and +U27 Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U27-Pad3_ d_and +U10 Net-_U10-Pad1_ Net-_U1-Pad11_ Net-_U10-Pad3_ d_and +U22 Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U22-Pad3_ d_and +U12 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U12-Pad3_ d_and +U23 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U23-Pad3_ d_and +U19 Net-_U10-Pad1_ Net-_U14-Pad2_ Net-_U19-Pad3_ d_and +U26 Net-_U19-Pad3_ Net-_U26-Pad2_ Net-_U26-Pad3_ d_and +U30 Net-_U26-Pad3_ Net-_U27-Pad3_ Net-_U30-Pad3_ d_or +U31 Net-_U22-Pad3_ Net-_U23-Pad3_ Net-_U31-Pad3_ d_or +U33 Net-_U30-Pad3_ Net-_U31-Pad3_ Net-_U1-Pad14_ d_or +U17 Net-_U1-Pad7_ Net-_U11-Pad2_ Net-_U17-Pad3_ d_and +U11 Net-_U1-Pad8_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and +U13 Net-_U1-Pad9_ Net-_U11-Pad2_ Net-_U13-Pad3_ d_and +U9 Net-_U1-Pad6_ Net-_U11-Pad2_ Net-_U26-Pad2_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT +U34 Net-_U1-Pad5_ Net-_U15-Pad2_ d_inverter +U35 Net-_U1-Pad10_ Net-_U11-Pad2_ d_inverter + +.end diff --git a/library/SubcircuitLibrary/74153/Dual4to1MUX.sch b/library/SubcircuitLibrary/74153/Dual4to1MUX.sch new file mode 100644 index 00000000..340b1a31 --- /dev/null +++ b/library/SubcircuitLibrary/74153/Dual4to1MUX.sch @@ -0,0 +1,814 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:74153-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U14 +U 1 1 5C936BFE +P 3850 2450 +F 0 "U14" H 3850 2450 60 0000 C CNN +F 1 "d_and" H 3900 2550 60 0000 C CNN +F 2 "" H 3850 2450 60 0000 C CNN +F 3 "" H 3850 2450 60 0000 C CNN + 1 3850 2450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U25 +U 1 1 5C936C8A +P 4850 2600 +F 0 "U25" H 4850 2600 60 0000 C CNN +F 1 "d_and" H 4900 2700 60 0000 C CNN +F 2 "" H 4850 2600 60 0000 C CNN +F 3 "" H 4850 2600 60 0000 C CNN + 1 4850 2600 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 5C936E84 +P 3800 3050 +F 0 "U5" H 3800 3050 60 0000 C CNN +F 1 "d_and" H 3850 3150 60 0000 C CNN +F 2 "" H 3800 3050 60 0000 C CNN +F 3 "" H 3800 3050 60 0000 C CNN + 1 3800 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U20 +U 1 1 5C936E8A +P 4800 3200 +F 0 "U20" H 4800 3200 60 0000 C CNN +F 1 "d_and" H 4850 3300 60 0000 C CNN +F 2 "" H 4800 3200 60 0000 C CNN +F 3 "" H 4800 3200 60 0000 C CNN + 1 4800 3200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 5C936EF6 +P 3800 3550 +F 0 "U7" H 3800 3550 60 0000 C CNN +F 1 "d_and" H 3850 3650 60 0000 C CNN +F 2 "" H 3800 3550 60 0000 C CNN +F 3 "" H 3800 3550 60 0000 C CNN + 1 3800 3550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U21 +U 1 1 5C936EFC +P 4800 3700 +F 0 "U21" H 4800 3700 60 0000 C CNN +F 1 "d_and" H 4850 3800 60 0000 C CNN +F 2 "" H 4800 3700 60 0000 C CNN +F 3 "" H 4800 3700 60 0000 C CNN + 1 4800 3700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U18 +U 1 1 5C936F88 +P 3950 1900 +F 0 "U18" H 3950 1900 60 0000 C CNN +F 1 "d_and" H 4000 2000 60 0000 C CNN +F 2 "" H 3950 1900 60 0000 C CNN +F 3 "" H 3950 1900 60 0000 C CNN + 1 3950 1900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U24 +U 1 1 5C936F8E +P 4850 2150 +F 0 "U24" H 4850 2150 60 0000 C CNN +F 1 "d_and" H 4900 2250 60 0000 C CNN +F 2 "" H 4850 2150 60 0000 C CNN +F 3 "" H 4850 2150 60 0000 C CNN + 1 4850 2150 + 1 0 0 -1 +$EndComp +$Comp +L d_or U28 +U 1 1 5C937316 +P 5900 2550 +F 0 "U28" H 5900 2550 60 0000 C CNN +F 1 "d_or" H 5900 2650 60 0000 C CNN +F 2 "" H 5900 2550 60 0000 C CNN +F 3 "" H 5900 2550 60 0000 C CNN + 1 5900 2550 + 1 0 0 -1 +$EndComp +$Comp +L d_or U29 +U 1 1 5C9373A8 +P 5900 2800 +F 0 "U29" H 5900 2800 60 0000 C CNN +F 1 "d_or" H 5900 2900 60 0000 C CNN +F 2 "" H 5900 2800 60 0000 C CNN +F 3 "" H 5900 2800 60 0000 C CNN + 1 5900 2800 + 1 0 0 -1 +$EndComp +$Comp +L d_or U32 +U 1 1 5C9373FC +P 6850 2650 +F 0 "U32" H 6850 2650 60 0000 C CNN +F 1 "d_or" H 6850 2750 60 0000 C CNN +F 2 "" H 6850 2650 60 0000 C CNN +F 3 "" H 6850 2650 60 0000 C CNN + 1 6850 2650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4400 1850 4400 2050 +Wire Wire Line + 4400 2500 4400 2400 +Wire Wire Line + 4400 2400 4300 2400 +Wire Wire Line + 4350 3100 4350 3000 +Wire Wire Line + 4350 3000 4250 3000 +Wire Wire Line + 4350 3600 4350 3500 +Wire Wire Line + 4350 3500 4250 3500 +Wire Wire Line + 6400 2550 6400 2500 +Wire Wire Line + 6400 2500 6350 2500 +Wire Wire Line + 6400 2650 6400 2750 +Wire Wire Line + 6400 2750 6350 2750 +Wire Wire Line + 5450 2450 5350 2450 +Wire Wire Line + 5350 2450 5350 2100 +Wire Wire Line + 5350 2100 5300 2100 +Wire Wire Line + 5300 2550 5450 2550 +Wire Wire Line + 5450 2700 5300 2700 +Wire Wire Line + 5300 2700 5300 3150 +Wire Wire Line + 5300 3150 5250 3150 +Wire Wire Line + 5250 3650 5400 3650 +Wire Wire Line + 5400 3650 5400 2800 +Wire Wire Line + 5400 2800 5450 2800 +$Comp +L d_inverter U2 +U 1 1 5C9378F6 +P 2650 1350 +F 0 "U2" H 2650 1250 60 0000 C CNN +F 1 "d_inverter" H 2650 1500 60 0000 C CNN +F 2 "" H 2700 1300 60 0000 C CNN +F 3 "" H 2700 1300 60 0000 C CNN + 1 2650 1350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 5C93798D +P 2700 950 +F 0 "U3" H 2700 850 60 0000 C CNN +F 1 "d_inverter" H 2700 1100 60 0000 C CNN +F 2 "" H 2750 900 60 0000 C CNN +F 3 "" H 2750 900 60 0000 C CNN + 1 2700 950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3500 1800 3100 1800 +Wire Wire Line + 3100 1350 3100 5600 +Wire Wire Line + 3500 1900 3200 1900 +Wire Wire Line + 3200 950 3200 5100 +Wire Wire Line + 2950 1350 3100 1350 +Connection ~ 3100 1800 +Wire Wire Line + 3000 950 3200 950 +Connection ~ 3200 1900 +Wire Wire Line + 1800 950 2400 950 +Wire Wire Line + 1800 1350 2350 1350 +Wire Wire Line + 2200 950 2200 6200 +Connection ~ 2200 950 +Wire Wire Line + 2300 1350 2300 6100 +$Comp +L d_and U15 +U 1 1 5C937C96 +P 3850 2700 +F 0 "U15" H 3850 2700 60 0000 C CNN +F 1 "d_and" H 3900 2800 60 0000 C CNN +F 2 "" H 3850 2700 60 0000 C CNN +F 3 "" H 3850 2700 60 0000 C CNN + 1 3850 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U6 +U 1 1 5C937CEE +P 3800 3300 +F 0 "U6" H 3800 3300 60 0000 C CNN +F 1 "d_and" H 3850 3400 60 0000 C CNN +F 2 "" H 3800 3300 60 0000 C CNN +F 3 "" H 3800 3300 60 0000 C CNN + 1 3800 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U8 +U 1 1 5C937D35 +P 3800 3800 +F 0 "U8" H 3800 3800 60 0000 C CNN +F 1 "d_and" H 3850 3900 60 0000 C CNN +F 2 "" H 3800 3800 60 0000 C CNN +F 3 "" H 3800 3800 60 0000 C CNN + 1 3800 3800 + 1 0 0 -1 +$EndComp +$Comp +L d_and U4 +U 1 1 5C937DC5 +P 3800 2150 +F 0 "U4" H 3800 2150 60 0000 C CNN +F 1 "d_and" H 3850 2250 60 0000 C CNN +F 2 "" H 3800 2150 60 0000 C CNN +F 3 "" H 3800 2150 60 0000 C CNN + 1 3800 2150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3350 2150 3300 2150 +Wire Wire Line + 3300 2150 3300 3800 +Wire Wire Line + 3300 2700 3400 2700 +Wire Wire Line + 3300 3300 3350 3300 +Connection ~ 3300 2700 +Wire Wire Line + 3000 3800 3350 3800 +Connection ~ 3300 3300 +Wire Wire Line + 4350 3200 4350 3250 +Wire Wire Line + 4350 3250 4250 3250 +Wire Wire Line + 4400 2600 4400 2650 +Wire Wire Line + 4400 2650 4300 2650 +Wire Wire Line + 4400 2150 4300 2150 +Wire Wire Line + 4300 2150 4300 2100 +Wire Wire Line + 4300 2100 4250 2100 +Wire Wire Line + 4350 3700 4250 3700 +Wire Wire Line + 4250 3700 4250 3750 +Wire Wire Line + 3350 3700 1600 3700 +Wire Wire Line + 3350 3200 1600 3200 +Wire Wire Line + 3400 2600 1600 2600 +Wire Wire Line + 3350 2050 1600 2050 +Wire Wire Line + 3000 3950 3000 3800 +Wire Wire Line + 2950 3950 3000 3950 +Wire Wire Line + 1600 3950 2350 3950 +Connection ~ 3300 3800 +$Comp +L d_and U16 +U 1 1 5C9388D0 +P 3850 5100 +F 0 "U16" H 3850 5100 60 0000 C CNN +F 1 "d_and" H 3900 5200 60 0000 C CNN +F 2 "" H 3850 5100 60 0000 C CNN +F 3 "" H 3850 5100 60 0000 C CNN + 1 3850 5100 + 1 0 0 -1 +$EndComp +$Comp +L d_and U27 +U 1 1 5C9388D6 +P 4850 5250 +F 0 "U27" H 4850 5250 60 0000 C CNN +F 1 "d_and" H 4900 5350 60 0000 C CNN +F 2 "" H 4850 5250 60 0000 C CNN +F 3 "" H 4850 5250 60 0000 C CNN + 1 4850 5250 + 1 0 0 -1 +$EndComp +$Comp +L d_and U10 +U 1 1 5C9388DC +P 3800 5700 +F 0 "U10" H 3800 5700 60 0000 C CNN +F 1 "d_and" H 3850 5800 60 0000 C CNN +F 2 "" H 3800 5700 60 0000 C CNN +F 3 "" H 3800 5700 60 0000 C CNN + 1 3800 5700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U22 +U 1 1 5C9388E2 +P 4800 5850 +F 0 "U22" H 4800 5850 60 0000 C CNN +F 1 "d_and" H 4850 5950 60 0000 C CNN +F 2 "" H 4800 5850 60 0000 C CNN +F 3 "" H 4800 5850 60 0000 C CNN + 1 4800 5850 + 1 0 0 -1 +$EndComp +$Comp +L d_and U12 +U 1 1 5C9388E8 +P 3800 6200 +F 0 "U12" H 3800 6200 60 0000 C CNN +F 1 "d_and" H 3850 6300 60 0000 C CNN +F 2 "" H 3800 6200 60 0000 C CNN +F 3 "" H 3800 6200 60 0000 C CNN + 1 3800 6200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U23 +U 1 1 5C9388EE +P 4800 6350 +F 0 "U23" H 4800 6350 60 0000 C CNN +F 1 "d_and" H 4850 6450 60 0000 C CNN +F 2 "" H 4800 6350 60 0000 C CNN +F 3 "" H 4800 6350 60 0000 C CNN + 1 4800 6350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U19 +U 1 1 5C9388F4 +P 3950 4550 +F 0 "U19" H 3950 4550 60 0000 C CNN +F 1 "d_and" H 4000 4650 60 0000 C CNN +F 2 "" H 3950 4550 60 0000 C CNN +F 3 "" H 3950 4550 60 0000 C CNN + 1 3950 4550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U26 +U 1 1 5C9388FA +P 4850 4800 +F 0 "U26" H 4850 4800 60 0000 C CNN +F 1 "d_and" H 4900 4900 60 0000 C CNN +F 2 "" H 4850 4800 60 0000 C CNN +F 3 "" H 4850 4800 60 0000 C CNN + 1 4850 4800 + 1 0 0 -1 +$EndComp +$Comp +L d_or U30 +U 1 1 5C938900 +P 5900 5200 +F 0 "U30" H 5900 5200 60 0000 C CNN +F 1 "d_or" H 5900 5300 60 0000 C CNN +F 2 "" H 5900 5200 60 0000 C CNN +F 3 "" H 5900 5200 60 0000 C CNN + 1 5900 5200 + 1 0 0 -1 +$EndComp +$Comp +L d_or U31 +U 1 1 5C938906 +P 5900 5450 +F 0 "U31" H 5900 5450 60 0000 C CNN +F 1 "d_or" H 5900 5550 60 0000 C CNN +F 2 "" H 5900 5450 60 0000 C CNN +F 3 "" H 5900 5450 60 0000 C CNN + 1 5900 5450 + 1 0 0 -1 +$EndComp +$Comp +L d_or U33 +U 1 1 5C93890C +P 6850 5300 +F 0 "U33" H 6850 5300 60 0000 C CNN +F 1 "d_or" H 6850 5400 60 0000 C CNN +F 2 "" H 6850 5300 60 0000 C CNN +F 3 "" H 6850 5300 60 0000 C CNN + 1 6850 5300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4400 4500 4400 4700 +Wire Wire Line + 4400 5150 4400 5050 +Wire Wire Line + 4400 5050 4300 5050 +Wire Wire Line + 4350 5750 4350 5650 +Wire Wire Line + 4350 5650 4250 5650 +Wire Wire Line + 4350 6250 4350 6150 +Wire Wire Line + 4350 6150 4250 6150 +Wire Wire Line + 6400 5200 6400 5150 +Wire Wire Line + 6400 5150 6350 5150 +Wire Wire Line + 6400 5300 6400 5400 +Wire Wire Line + 6400 5400 6350 5400 +Wire Wire Line + 5450 5100 5350 5100 +Wire Wire Line + 5350 5100 5350 4750 +Wire Wire Line + 5350 4750 5300 4750 +Wire Wire Line + 5300 5200 5450 5200 +Wire Wire Line + 5450 5350 5300 5350 +Wire Wire Line + 5300 5350 5300 5800 +Wire Wire Line + 5300 5800 5250 5800 +Wire Wire Line + 5250 6300 5400 6300 +Wire Wire Line + 5400 6300 5400 5450 +Wire Wire Line + 5400 5450 5450 5450 +Wire Wire Line + 3100 4450 3500 4450 +Wire Wire Line + 3200 4550 3500 4550 +$Comp +L d_and U17 +U 1 1 5C938937 +P 3850 5350 +F 0 "U17" H 3850 5350 60 0000 C CNN +F 1 "d_and" H 3900 5450 60 0000 C CNN +F 2 "" H 3850 5350 60 0000 C CNN +F 3 "" H 3850 5350 60 0000 C CNN + 1 3850 5350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U11 +U 1 1 5C93893D +P 3800 5950 +F 0 "U11" H 3800 5950 60 0000 C CNN +F 1 "d_and" H 3850 6050 60 0000 C CNN +F 2 "" H 3800 5950 60 0000 C CNN +F 3 "" H 3800 5950 60 0000 C CNN + 1 3800 5950 + 1 0 0 -1 +$EndComp +$Comp +L d_and U13 +U 1 1 5C938943 +P 3800 6450 +F 0 "U13" H 3800 6450 60 0000 C CNN +F 1 "d_and" H 3850 6550 60 0000 C CNN +F 2 "" H 3800 6450 60 0000 C CNN +F 3 "" H 3800 6450 60 0000 C CNN + 1 3800 6450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U9 +U 1 1 5C938949 +P 3800 4800 +F 0 "U9" H 3800 4800 60 0000 C CNN +F 1 "d_and" H 3850 4900 60 0000 C CNN +F 2 "" H 3800 4800 60 0000 C CNN +F 3 "" H 3800 4800 60 0000 C CNN + 1 3800 4800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3350 4800 3300 4800 +Wire Wire Line + 3300 4800 3300 6450 +Wire Wire Line + 3300 5350 3400 5350 +Wire Wire Line + 3300 5950 3350 5950 +Connection ~ 3300 5350 +Wire Wire Line + 3200 6450 3350 6450 +Connection ~ 3300 5950 +Wire Wire Line + 4350 5850 4350 5900 +Wire Wire Line + 4350 5900 4250 5900 +Wire Wire Line + 4400 5250 4400 5300 +Wire Wire Line + 4400 5300 4300 5300 +Wire Wire Line + 4400 4800 4300 4800 +Wire Wire Line + 4300 4800 4300 4750 +Wire Wire Line + 4300 4750 4250 4750 +Wire Wire Line + 4350 6350 4250 6350 +Wire Wire Line + 4250 6350 4250 6400 +Wire Wire Line + 3350 6350 1600 6350 +Wire Wire Line + 3350 5850 1600 5850 +Wire Wire Line + 3400 5250 1600 5250 +Wire Wire Line + 3350 4700 1600 4700 +Wire Wire Line + 3200 6600 3200 6450 +Wire Wire Line + 3000 6600 3200 6600 +Wire Wire Line + 1600 6600 2400 6600 +Connection ~ 3300 6450 +Connection ~ 2300 1350 +Connection ~ 3100 4450 +Connection ~ 3200 4550 +$Comp +L PORT U1 +U 1 1 5C93A0F9 +P 1350 2050 +F 0 "U1" H 1400 2150 30 0000 C CNN +F 1 "PORT" H 1350 2050 30 0000 C CNN +F 2 "" H 1350 2050 60 0000 C CNN +F 3 "" H 1350 2050 60 0000 C CNN + 1 1350 2050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C93A174 +P 1350 4700 +F 0 "U1" H 1400 4800 30 0000 C CNN +F 1 "PORT" H 1350 4700 30 0000 C CNN +F 2 "" H 1350 4700 60 0000 C CNN +F 3 "" H 1350 4700 60 0000 C CNN + 6 1350 4700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C93AA3C +P 1350 2600 +F 0 "U1" H 1400 2700 30 0000 C CNN +F 1 "PORT" H 1350 2600 30 0000 C CNN +F 2 "" H 1350 2600 60 0000 C CNN +F 3 "" H 1350 2600 60 0000 C CNN + 2 1350 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C93AACB +P 1350 3200 +F 0 "U1" H 1400 3300 30 0000 C CNN +F 1 "PORT" H 1350 3200 30 0000 C CNN +F 2 "" H 1350 3200 60 0000 C CNN +F 3 "" H 1350 3200 60 0000 C CNN + 3 1350 3200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C93AB5F +P 1350 3700 +F 0 "U1" H 1400 3800 30 0000 C CNN +F 1 "PORT" H 1350 3700 30 0000 C CNN +F 2 "" H 1350 3700 60 0000 C CNN +F 3 "" H 1350 3700 60 0000 C CNN + 4 1350 3700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5C93AD97 +P 1350 5250 +F 0 "U1" H 1400 5350 30 0000 C CNN +F 1 "PORT" H 1350 5250 30 0000 C CNN +F 2 "" H 1350 5250 60 0000 C CNN +F 3 "" H 1350 5250 60 0000 C CNN + 7 1350 5250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5C93ADFC +P 1350 5850 +F 0 "U1" H 1400 5950 30 0000 C CNN +F 1 "PORT" H 1350 5850 30 0000 C CNN +F 2 "" H 1350 5850 60 0000 C CNN +F 3 "" H 1350 5850 60 0000 C CNN + 8 1350 5850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5C93AE63 +P 1350 6350 +F 0 "U1" H 1400 6450 30 0000 C CNN +F 1 "PORT" H 1350 6350 30 0000 C CNN +F 2 "" H 1350 6350 60 0000 C CNN +F 3 "" H 1350 6350 60 0000 C CNN + 9 1350 6350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C93AECA +P 1350 3950 +F 0 "U1" H 1400 4050 30 0000 C CNN +F 1 "PORT" H 1350 3950 30 0000 C CNN +F 2 "" H 1350 3950 60 0000 C CNN +F 3 "" H 1350 3950 60 0000 C CNN + 5 1350 3950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5C93AF79 +P 1350 6600 +F 0 "U1" H 1400 6700 30 0000 C CNN +F 1 "PORT" H 1350 6600 30 0000 C CNN +F 2 "" H 1350 6600 60 0000 C CNN +F 3 "" H 1350 6600 60 0000 C CNN + 10 1350 6600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5C93B10A +P 1550 950 +F 0 "U1" H 1600 1050 30 0000 C CNN +F 1 "PORT" H 1550 950 30 0000 C CNN +F 2 "" H 1550 950 60 0000 C CNN +F 3 "" H 1550 950 60 0000 C CNN + 11 1550 950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5C93B179 +P 1550 1350 +F 0 "U1" H 1600 1450 30 0000 C CNN +F 1 "PORT" H 1550 1350 30 0000 C CNN +F 2 "" H 1550 1350 60 0000 C CNN +F 3 "" H 1550 1350 60 0000 C CNN + 12 1550 1350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7300 2600 7600 2600 +Wire Wire Line + 7300 5250 7650 5250 +$Comp +L PORT U1 +U 13 1 5C93B567 +P 7850 2600 +F 0 "U1" H 7900 2700 30 0000 C CNN +F 1 "PORT" H 7850 2600 30 0000 C CNN +F 2 "" H 7850 2600 60 0000 C CNN +F 3 "" H 7850 2600 60 0000 C CNN + 13 7850 2600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5C93B5DA +P 7900 5250 +F 0 "U1" H 7950 5350 30 0000 C CNN +F 1 "PORT" H 7900 5250 30 0000 C CNN +F 2 "" H 7900 5250 60 0000 C CNN +F 3 "" H 7900 5250 60 0000 C CNN + 14 7900 5250 + -1 0 0 1 +$EndComp +Connection ~ 2200 3450 +Wire Wire Line + 3200 5100 3400 5100 +Wire Wire Line + 3400 5000 2300 5000 +Connection ~ 2300 5000 +Wire Wire Line + 3100 5600 3350 5600 +Wire Wire Line + 2200 5700 3350 5700 +Wire Wire Line + 2200 6200 3350 6200 +Connection ~ 2200 5700 +Wire Wire Line + 2300 6100 3350 6100 +Wire Wire Line + 3400 2450 3200 2450 +Connection ~ 3200 2450 +Wire Wire Line + 3400 2350 2300 2350 +Connection ~ 2300 2350 +Wire Wire Line + 3350 3050 2200 3050 +Connection ~ 2200 3050 +Wire Wire Line + 3350 2950 3100 2950 +Connection ~ 3100 2950 +Wire Wire Line + 3350 3450 2300 3450 +Wire Wire Line + 2300 3450 2300 3400 +Connection ~ 2300 3400 +Wire Wire Line + 3350 3550 2200 3550 +Connection ~ 2200 3550 +$Comp +L d_inverter U34 +U 1 1 5C95C9D0 +P 2650 3950 +F 0 "U34" H 2650 3850 60 0000 C CNN +F 1 "d_inverter" H 2650 4100 60 0000 C CNN +F 2 "" H 2700 3900 60 0000 C CNN +F 3 "" H 2700 3900 60 0000 C CNN + 1 2650 3950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U35 +U 1 1 5C95CD17 +P 2700 6600 +F 0 "U35" H 2700 6500 60 0000 C CNN +F 1 "d_inverter" H 2700 6750 60 0000 C CNN +F 2 "" H 2750 6550 60 0000 C CNN +F 3 "" H 2750 6550 60 0000 C CNN + 1 2700 6600 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74153/analysis b/library/SubcircuitLibrary/74153/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/74153/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file |