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authorrahulp132020-03-03 05:31:58 +0530
committerrahulp132020-03-03 05:31:58 +0530
commitdfc268e0863c913a1b8726cd54eea3b40caf7c67 (patch)
tree1cd82634684da5ae86b558d44756189e080545d4 /Windows/spice/examples/xspice/original-examples/rtlinv.in
parentfd62c52150c7d1f81da8060b2f5db6b94d174ccf (diff)
downloadeSim-dfc268e0863c913a1b8726cd54eea3b40caf7c67.tar.gz
eSim-dfc268e0863c913a1b8726cd54eea3b40caf7c67.tar.bz2
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upgrade ngspice to v31
Diffstat (limited to 'Windows/spice/examples/xspice/original-examples/rtlinv.in')
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diff --git a/Windows/spice/examples/xspice/original-examples/rtlinv.in b/Windows/spice/examples/xspice/original-examples/rtlinv.in
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+++ b/Windows/spice/examples/xspice/original-examples/rtlinv.in
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+rtlinv ckt - cascaded rtl inverters
+.width in=72
+.opt acct list node lvlcod=2
+.dc vin 0.0 2.5 0.025
+.tran 2ns 200ns
+vcc 6 0 5
+vin 1 0 pulse(0 5 2ns 2ns 2ns 80ns)
+rb1 1 2 10k
+rc1 6 3 1k
+q1 3 2 0 qnd
+rb2 3 4 10k
+q2 5 4 0 qnd
+rc2 6 5 1k
+.model qnd npn(bf=50 rb=70 rc=40 ccs=2pf tf=0.1ns tr=10ns cje=0.9pf
++ cjc=1.5pf pc=0.85 va=50)
+.print dc v(3) v(5)
+.plot dc v(3)
+.print tran v(3) v(5)
+.plot tran v(3) v(5) v(1)
+.end