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authorrahulp132020-03-03 05:31:58 +0530
committerrahulp132020-03-03 05:31:58 +0530
commitdfc268e0863c913a1b8726cd54eea3b40caf7c67 (patch)
tree1cd82634684da5ae86b558d44756189e080545d4 /Windows/spice/examples/vdmos/IXTP6N100D2-cap.cir
parentfd62c52150c7d1f81da8060b2f5db6b94d174ccf (diff)
downloadeSim-dfc268e0863c913a1b8726cd54eea3b40caf7c67.tar.gz
eSim-dfc268e0863c913a1b8726cd54eea3b40caf7c67.tar.bz2
eSim-dfc268e0863c913a1b8726cd54eea3b40caf7c67.zip
upgrade ngspice to v31
Diffstat (limited to 'Windows/spice/examples/vdmos/IXTP6N100D2-cap.cir')
-rw-r--r--Windows/spice/examples/vdmos/IXTP6N100D2-cap.cir18
1 files changed, 18 insertions, 0 deletions
diff --git a/Windows/spice/examples/vdmos/IXTP6N100D2-cap.cir b/Windows/spice/examples/vdmos/IXTP6N100D2-cap.cir
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index 00000000..de49a542
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+++ b/Windows/spice/examples/vdmos/IXTP6N100D2-cap.cir
@@ -0,0 +1,18 @@
+Test of VDMOS gate-source and gate-drain capacitance
+
+m1 d g s IXTP6N100D2
+
+.MODEL IXTP6N100D2 VDMOS(KP=2.9 RS=0.1 RD=1.3 RG=1 VTO=-2.7 LAMBDA=0.03 CGDMAX=3000p CGDMIN=2p CGS=2915p a=1 TT=1371n IS=2.13E-08 N=1.564 RB=0.0038 m=0.548 Vj=0.1 Cjo=3200pF ksubthres=0.1)
+
+vd d 0 dc 5
+vg g 0 pwl (0 -3 1 3)
+vs s 0 0
+
+.control
+save all @m1[cgd] @m1[cgs]
+tran 1m 1
+plot vs#branch
+plot @m1[cgd] @m1[cgs]
+.endc
+
+.end \ No newline at end of file