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| author | Rahul Paknikar | 2021-01-08 12:47:23 +0530 |
|---|---|---|
| committer | GitHub | 2021-01-08 12:47:23 +0530 |
| commit | e6f48f5b1bf22a1d048b44ed4416b4315a461306 (patch) | |
| tree | fd357549a236cdc652f0b6d2919beee0cee7faa5 /Windows/spice/examples/p-to-n-examples/switch-invs.lib | |
| parent | ac223c4a69c701ad0a247401acdc48b8b6b6dba6 (diff) | |
| parent | 6b512cbf954273b0f21d3800d10a7ad42a759425 (diff) | |
| download | eSim-e6f48f5b1bf22a1d048b44ed4416b4315a461306.tar.gz eSim-e6f48f5b1bf22a1d048b44ed4416b4315a461306.tar.bz2 eSim-e6f48f5b1bf22a1d048b44ed4416b4315a461306.zip | |
Merge pull request #161 from rahulp13/installersi2.1
fixed key issue for ubuntu 20+; updated installers for windows os
Diffstat (limited to 'Windows/spice/examples/p-to-n-examples/switch-invs.lib')
| -rw-r--r-- | Windows/spice/examples/p-to-n-examples/switch-invs.lib | 72 |
1 files changed, 0 insertions, 72 deletions
diff --git a/Windows/spice/examples/p-to-n-examples/switch-invs.lib b/Windows/spice/examples/p-to-n-examples/switch-invs.lib deleted file mode 100644 index 4a1eaaf2..00000000 --- a/Windows/spice/examples/p-to-n-examples/switch-invs.lib +++ /dev/null @@ -1,72 +0,0 @@ -* sw like an NMOS inverter with resistive load -.subckt invertern In Out VDD DGND -*sp out vdd in vdd swswitch on -Rl out vdd 10k -Cl out dgnd 0.1p -*C2 out vdd 0.1p -sn out dgnd in dgnd swswitch off -.ends invertern - -* sw like a PMOS inverter with resistive load -.subckt inverterp In Out VDD DGND -sp out vdd vdd in swswitch -Rl out 0 10k -*Cl out dgnd 0.1p -C2 out vdd 0.1p -*sn out dgnd in dgnd swswitch off -.ends inverterp - -* sw like a CMOS inverter -.subckt inverter In Out VDD DGND -sp out vdd vdd in swswitch -Rin in 0 1e9 -Cl out dgnd 0.1p -C2 out vdd 0.1p -sn out dgnd in dgnd swswitch -.ends inverter - -.model swswitch sw (vt=1 vh=0.1 ron=1k roff=1e12) -.model switchn sw (vt=1 vh=0.1 ron=1k roff=1e12) - -* sw like a CMOS inverter with PSPICE VSWITCH -.subckt invertervs In Out VDD DGND -sp out vdd vdd in swn -Rin in 0 1e9 -Cl out dgnd 0.1p -C2 out vdd 0.1p -sn out dgnd in dgnd swn -.ends invertervs - -.MODEL SWN VSWITCH ( VON = 1.1 VOFF = 0.9 RON=1k ROFF=1e12 ) - - -* sw like a CMOS inverter with PSPICE VSWITCH -.subckt invertervs2 In Out VDD DGND -sp out vdd vdd in swn -Rin in 0 1e9 -Cl out dgnd 0.1p -C2 out vdd 0.1p -sn out dgnd in dgnd swn -.MODEL SWN VSWITCH ( VON = 1.1 VOFF = 0.9 RON=1k ROFF=1e12 ) -.ends invertervs2 - -* sw like a CMOS inverter with PSPICE VSWITCH -.subckt invertervs3 In Out VDD DGND -sp out vdd vdd in swn2 -Rin in 0 1e9 -Cl out dgnd 0.1p -C2 out vdd 0.1p -sn out dgnd in dgnd swn2 -.ends invertervs3 - -.MODEL SWN2 VSWITCH ( VON = 1.1 VOFF = 0.9 RON=1k ROFF=1e12 ) - -* sw like a CMOS inverter with PSPICE VSWITCH -.subckt invertervs4 In Out VDD DGND -sp out vdd vdd in swn -Rin in 0 1e9 -Cl out dgnd 0.1p -C2 out vdd 0.1p -sn out dgnd in dgnd swn -.MODEL SWN VSWITCH ( VON = 1.1 VOFF = 0.9 RON=2k ROFF=1e12 ) -.ends invertervs4 |