initial commit

13 files changed, 528 insertions, 0 deletions

diff --git a/Windows/spice/examples/cider/serial/astable.cir b/Windows/spice/examples/cider/serial/astable.cir
new file mode 100644
index 00000000..c04c6bba
--- /dev/null
+++ b/Windows/spice/examples/cider/serial/astable.cir
@@ -0,0 +1,30 @@
+ASTABLE MULTIVIBRATOR
+
+VIN 5 0 DC 0 PULSE(0 5 0 1US 1US 100US 100US)
+VCC 6 0 5.0
+RC1 6 1 1K
+RC2 6 2 1K
+RB1 6 3 30K
+RB2 5 4 30K
+C1 1 4 150PF
+C2 2 3 150PF
+Q1 1 3 0 QMOD AREA = 100P
+Q2 2 4 0 QMOD AREA = 100P
+
+.OPTION ACCT BYPASS=1
+.TRAN 0.05US 8US 0US 0.05US
+.PRINT TRAN V(1) V(2) V(3) V(4)
+
+.MODEL QMOD NBJT LEVEL=1
++ X.MESH NODE=1  LOC=0.0
++ X.MESH NODE=61 LOC=3.0
++ REGION NUM=1 MATERIAL=1
++ MATERIAL NUM=1 SILICON NBGNN=1E17 NBGNP=1E17
++ MOBILITY MATERIAL=1 CONCMOD=SG FIELDMOD=SG
++ DOPING UNIF N.TYPE CONC=1E17 X.L=0.0 X.H=1.0
++ DOPING UNIF P.TYPE CONC=1E16 X.L=0.0 X.H=1.5
++ DOPING UNIF N.TYPE CONC=1E15 X.L=0.0 X.H=3.0
++ MODELS BGNW SRH CONCTAU AUGER CONCMOB FIELDMOB
++ OPTIONS BASE.LENGTH=1.0 BASE.DEPTH=1.25
+
+.END
diff --git a/Windows/spice/examples/cider/serial/charge.cir b/Windows/spice/examples/cider/serial/charge.cir
new file mode 100644
index 00000000..c4c689b6
--- /dev/null
+++ b/Windows/spice/examples/cider/serial/charge.cir
@@ -0,0 +1,53 @@
+MOS CHARGE PUMP
+
+VIN 4 0 DC 0V PULSE 0 5 15NS 5NS 5NS 50NS 100NS
+VDD 5 6 DC 0V PULSE 0 5 25NS 5NS 5NS 50NS 100NS
+VBB 0 7 DC 0V PULSE 0 5  0NS 5NS 5NS 50NS 100NS
+RD 6 2 10K
+M1 5 4 3 7 MMOD W=100UM
+VS 3 2 0
+VC 2 1 0
+C2 1 0 10PF
+
+.IC V(3)=1.0
+.TRAN 2NS 200NS
+.OPTIONS ACCT BYPASS=1
+.PRINT TRAN V(1) V(2)
+
+.MODEL MMOD NUMOS
++ X.MESH N=1 L=0
++ X.MESH N=3 L=0.4
++ X.MESH N=7 L=0.6
++ X.MESH N=15 L=1.4
++ X.MESH N=19 L=1.6
++ X.MESH N=21 L=2.0
++
++ Y.MESH N=1 L=0
++ Y.MESH N=4 L=0.015
++ Y.MESH N=8 L=0.05
++ Y.MESH N=12 L=0.25
++ Y.MESH N=14 L=0.35
++ Y.MESH N=17 L=0.5
++ Y.MESH N=21 L=1.0
++
++ REGION NUM=1 MATERIAL=1 Y.L=0.015
++ MATERIAL NUM=1 SILICON
++ MOBILITY MATERIAL=1 CONCMOD=SG FIELDMOD=SG
++
++ REGION NUM=2 MATERIAL=2 Y.H=0.015 X.L=0.5 X.H=1.5
++ MATERIAL NUM=2 OXIDE
++
++ ELEC NUM=1 IX.L=18 IX.H=21   IY.L=4  IY.H=4
++ ELEC NUM=2 IX.L=5  IX.H=17   IY.L=1  IY.H=1
++ ELEC NUM=3 IX.L=1  IX.H=4    IY.L=4  IY.H=4
++ ELEC NUM=4 IX.L=1  IX.H=21   IY.L=21 IY.H=21
++
++ DOPING UNIF N.TYPE CONC=1E18   X.L=0.0 X.H=0.5 Y.L=0.015 Y.H=0.25
++ DOPING UNIF N.TYPE CONC=1E18   X.L=1.5 X.H=2.0 Y.L=0.015 Y.H=0.25
++ DOPING UNIF P.TYPE CONC=1E15   X.L=0.0 X.H=2.0 Y.L=0.015 Y.H=1.0
++ DOPING UNIF P.TYPE CONC=1.3E17 X.L=0.5 X.H=1.5 Y.L=0.015 Y.H=0.05
++
++ MODELS CONCMOB FIELDMOB
++ METHOD ONEC
+
+.END
diff --git a/Windows/spice/examples/cider/serial/colposc.cir b/Windows/spice/examples/cider/serial/colposc.cir
new file mode 100644
index 00000000..b7d14ce9
--- /dev/null
+++ b/Windows/spice/examples/cider/serial/colposc.cir
@@ -0,0 +1,29 @@
+COLPITT'S OSCILLATOR CIRCUIT
+
+R1 1 0 1
+Q1 2 1 3 QMOD AREA = 100P
+VCC 4 0 5 
+RL 4 2 750
+C1 2 3 500P
+C2 4 3 4500P
+L1 4 2 5UH
+RE 3 6 4.65K
+VEE 6 0 DC -15 PWL 0 -15 1E-9 -10 
+
+.TRAN 30N 12U
+.PRINT TRAN V(2)
+
+.MODEL QMOD NBJT LEVEL=1
++ X.MESH NODE=1  LOC=0.0
++ X.MESH NODE=61 LOC=3.0
++ REGION NUM=1 MATERIAL=1
++ MATERIAL NUM=1 SILICON NBGNN=1E17 NBGNP=1E17
++ MOBILITY MATERIAL=1 CONCMOD=SG FIELDMOD=SG
++ DOPING UNIF N.TYPE CONC=1E17 X.L=0.0 X.H=1.0
++ DOPING UNIF P.TYPE CONC=1E16 X.L=0.0 X.H=1.5
++ DOPING UNIF N.TYPE CONC=1E15 X.L=0.0 X.H=3.0
++ MODELS BGNW SRH CONCTAU AUGER CONCMOB FIELDMOB
++ OPTIONS BASE.LENGTH=1.0 BASE.DEPTH=1.25
+
+.OPTIONS ACCT BYPASS=1
+.END
diff --git a/Windows/spice/examples/cider/serial/dbridge.cir b/Windows/spice/examples/cider/serial/dbridge.cir
new file mode 100644
index 00000000..052ae4f0
--- /dev/null
+++ b/Windows/spice/examples/cider/serial/dbridge.cir
@@ -0,0 +1,30 @@
+DIODE BRIDGE RECTIFIER
+
+VLINE 3 4 0.0V SIN 0V 10V 60HZ
+VGRND 2 0 0.0V 
+D1 3 1 M_PN AREA=100
+D2 4 1 M_PN AREA=100
+D3 2 3 M_PN AREA=100
+D4 2 4 M_PN AREA=100
+RL 1 2 1.0K
+
+.MODEL M_PN NUMD LEVEL=1
++ ***************************************
++ *** ONE-DIMENSIONAL NUMERICAL DIODE ***
++ ***************************************
++ OPTIONS DEFA=1P
++ X.MESH LOC=0.0 N=1
++ X.MESH LOC=30.0 N=201
++ DOMAIN   NUM=1 MATERIAL=1
++ MATERIAL NUM=1 SILICON
++ MOBILITY MAT=1 CONCMOD=CT FIELDMOD=CT
++ DOPING GAUSS P.TYPE CONC=1E20 X.L=0.0  X.H=0.0 CHAR.L=1.0
++ DOPING UNIF  N.TYPE CONC=1E14 X.L=0.0  X.H=30.0
++ DOPING GAUSS N.TYPE CONC=5E19 X.L=30.0  X.H=30.0 CHAR.L=2.0 
++ MODELS BGN ^AVAL SRH AUGER CONCTAU CONCMOB FIELDMOB
++ METHOD AC=DIRECT
+
+.OPTION ACCT BYPASS=1 METHOD=GEAR
+.TRAN 0.5MS 50MS
+.PRINT I(VLINE)
+.END
diff --git a/Windows/spice/examples/cider/serial/invchain.cir b/Windows/spice/examples/cider/serial/invchain.cir
new file mode 100644
index 00000000..c05513a0
--- /dev/null
+++ b/Windows/spice/examples/cider/serial/invchain.cir
@@ -0,0 +1,34 @@
+4 STAGE RTL INVERTER CHAIN
+
+VIN 1 0 DC 0V PWL 0NS 0V 1NS 5V
+VCC 12 0 DC 5.0V
+RC1 12 3 2.5K
+RB1 1 2 8K
+Q1 3 2 0 QMOD AREA = 100P
+RB2 3 4 8K
+RC2 12 5 2.5K
+Q2 5 4 0 QMOD AREA = 100P
+RB3 5 6 8K
+RC3 12 7 2.5K
+Q3 7 6 0 QMOD AREA = 100P
+RB4 7 8 8K
+RC4 12 9 2.5K
+Q4 9 8 0 QMOD AREA = 100P
+
+.PRINT TRAN V(3) V(5) V(9)
+.TRAN 1E-9 10E-9
+
+.MODEL QMOD NBJT LEVEL=1
++ X.MESH NODE=1  LOC=0.0
++ X.MESH NODE=61 LOC=3.0
++ REGION NUM=1 MATERIAL=1
++ MATERIAL NUM=1 SILICON NBGNN=1E17 NBGNP=1E17
++ MOBILITY MATERIAL=1 CONCMOD=SG FIELDMOD=SG
++ DOPING UNIF N.TYPE CONC=1E17 X.L=0.0 X.H=1.0
++ DOPING UNIF P.TYPE CONC=1E16 X.L=0.0 X.H=1.5
++ DOPING UNIF N.TYPE CONC=1E15 X.L=0.0 X.H=3.0
++ MODELS BGNW SRH CONCTAU AUGER CONCMOB FIELDMOB
++ OPTIONS BASE.LENGTH=1.0 BASE.DEPTH=1.25
+
+.OPTION ACCT BYPASS=1
+.END
diff --git a/Windows/spice/examples/cider/serial/meclgate.cir b/Windows/spice/examples/cider/serial/meclgate.cir
new file mode 100644
index 00000000..7f5e88ba
--- /dev/null
+++ b/Windows/spice/examples/cider/serial/meclgate.cir
@@ -0,0 +1,70 @@
+MOTOROLA MECL III ECL GATE
+*.DC VIN -2.0 0 0.02
+.TRAN 0.2NS 20NS
+VEE 22 0 -6.0
+VIN 1 0 PULSE -0.8 -1.8 0.2NS 0.2NS 0.2NS 10NS 20NS
+RS 1 2 50
+Q1 4 2 6 QMOD AREA = 100P
+Q2 4 3 6 QMOD AREA = 100P
+Q3 5 7 6 QMOD AREA = 100P
+Q4 0 8 7 QMOD AREA = 100P
+
+D1 8 9 DMOD
+D2 9 10 DMOD
+
+RP1 3 22 50K
+RC1 0 4 100
+RC2 0 5 112
+RE 6 22 380
+R1 7 22 2K
+R2 0 8 350
+R3 10 22 1958
+
+Q5 0 5 11 QMOD AREA = 100P
+Q6 0 4 12 QMOD AREA = 100P
+
+RP2 11 22 560
+RP3 12 22 560
+
+Q7 13 12 15 QMOD AREA = 100P
+Q8 14 16 15 QMOD AREA = 100P
+
+RE2 15 22 380
+RC3 0 13 100
+RC4 0 14 112
+
+Q9 0 17 16 QMOD AREA = 100P
+
+R4 16 22 2K
+R5 0 17 350
+D3 17 18 DMOD
+D4 18 19 DMOD
+R6 19 22 1958
+
+Q10 0 14 20 QMOD AREA = 100P
+Q11 0 13 21 QMOD AREA = 100P
+
+RP4 20 22 560
+RP5 21 22 560
+
+.MODEL DMOD D RS=40 TT=0.1NS CJO=0.9PF N=1 IS=1E-14 EG=1.11 VJ=0.8 M=0.5
+
+.MODEL QMOD NBJT LEVEL=1
++ X.MESH NODE=1  LOC=0.0
++ X.MESH NODE=10 LOC=0.9
++ X.MESH NODE=20 LOC=1.1
++ X.MESH NODE=30 LOC=1.4
++ X.MESH NODE=40 LOC=1.6
++ X.MESH NODE=61 LOC=3.0
++ REGION NUM=1 MATERIAL=1
++ MATERIAL NUM=1 SILICON NBGNN=1E17 NBGNP=1E17
++ MOBILITY MATERIAL=1 CONCMOD=SG FIELDMOD=SG
++ DOPING UNIF N.TYPE CONC=1E17 X.L=0.0 X.H=1.0
++ DOPING UNIF P.TYPE CONC=1E16 X.L=0.0 X.H=1.5
++ DOPING UNIF N.TYPE CONC=1E15 X.L=0.0 X.H=3.0
++ MODELS BGNW SRH CONCTAU AUGER CONCMOB FIELDMOB
++ OPTIONS BASE.LENGTH=1.0 BASE.DEPTH=1.25
+
+.OPTIONS ACCT BYPASS=1
+.PRINT TRAN V(12) V(21)
+.END
diff --git a/Windows/spice/examples/cider/serial/nmosinv.cir b/Windows/spice/examples/cider/serial/nmosinv.cir
new file mode 100644
index 00000000..b6fa11ab
--- /dev/null
+++ b/Windows/spice/examples/cider/serial/nmosinv.cir
@@ -0,0 +1,51 @@
+RESISTIVE LOAD NMOS INVERTER
+VIN 1 0 PWL 0 0.0 2NS 5
+VDD 3 0 DC 5.0
+RD 3 2 2.5K
+M1 2 1 4 5 MMOD W=10UM
+CL 2 0 2PF
+VB 5 0 0
+VS 4 0 0
+
+.MODEL MMOD NUMOS
++ X.MESH L=0.0 N=1
++ X.MESH L=0.6 N=4
++ X.MESH L=0.7 N=5
++ X.MESH L=1.0 N=7
++ X.MESH L=1.2 N=11
++ X.MESH L=3.2 N=21
++ X.MESH L=3.4 N=25
++ X.MESH L=3.7 N=27
++ X.MESH L=3.8 N=28
++ X.MESH L=4.4 N=31
++
++ Y.MESH L=-.05 N=1
++ Y.MESH L=0.0  N=5
++ Y.MESH L=.05  N=9
++ Y.MESH L=0.3  N=14
++ Y.MESH L=2.0  N=19
++
++ REGION NUM=1 MATERIAL=1 Y.L=0.0
++ MATERIAL NUM=1 SILICON
++ MOBILITY MATERIAL=1 CONCMOD=SG FIELDMOD=SG
++
++ REGION NUM=2 MATERIAL=2 Y.H=0.0 X.L=0.7 X.H=3.7
++ MATERIAL NUM=2 OXIDE
++
++ ELEC NUM=1 X.L=3.8 X.H=4.4	Y.L=0.0 Y.H=0.0
++ ELEC NUM=2 X.L=0.7 X.H=3.7	IY.L=1  IY.H=1
++ ELEC NUM=3 X.L=0.0 X.H=0.6	Y.L=0.0 Y.H=0.0
++ ELEC NUM=4 X.L=0.0 X.H=4.4	Y.L=2.0 Y.H=2.0
++
++ DOPING UNIF P.TYPE CONC=2.5E16 X.L=0.0 X.H=4.4  Y.L=0.0 Y.H=2.0
++ DOPING UNIF P.TYPE CONC=1E16   X.L=0.0 X.H=4.4  Y.L=0.0 Y.H=0.05
++ DOPING UNIF N.TYPE CONC=1E20   X.L=0.0 X.H=1.1  Y.L=0.0 Y.H=0.2
++ DOPING UNIF N.TYPE CONC=1E20   X.L=3.3 X.H=4.4  Y.L=0.0 Y.H=0.2
++
++ MODELS CONCMOB FIELDMOB
++ METHOD AC=DIRECT ONEC
+
+.TRAN 0.2NS 30NS
+.OPTIONS ACCT BYPASS=1
+.PRINT TRAN V(1) V(2)
+.END
diff --git a/Windows/spice/examples/cider/serial/pass.cir b/Windows/spice/examples/cider/serial/pass.cir
new file mode 100644
index 00000000..a15a6f61
--- /dev/null
+++ b/Windows/spice/examples/cider/serial/pass.cir
@@ -0,0 +1,55 @@
+TURNOFF TRANSIENT OF PASS TRANSISTOR
+
+M1 11 2 3 4 MMOD W=20UM
+CS 1 0 6.0PF
+CL 3 0 6.0PF
+R1 3 6 200K
+VIN 6 0 DC 0
+VDRN 1 11 DC 0
+VG 2 0 DC 5 PWL 0 5 0.1N 0 1 0
+VB 4 0 DC 0.0
+
+.TRAN 0.05NS 0.2NS 0.0NS 0.05NS
+.PRINT TRAN V(1) I(VDRN)
+.IC V(1)=0 V(3)=0
+.OPTION ACCT BYPASS=1
+
+.MODEL MMOD NUMOS
++ X.MESH L=0.0 N=1
++ X.MESH L=0.6 N=4
++ X.MESH L=0.7 N=5
++ X.MESH L=1.0 N=7
++ X.MESH L=1.2 N=11
++ X.MESH L=3.2 N=21
++ X.MESH L=3.4 N=25
++ X.MESH L=3.7 N=27
++ X.MESH L=3.8 N=28
++ X.MESH L=4.4 N=31
++
++ Y.MESH L=-.05 N=1
++ Y.MESH L=0.0  N=5
++ Y.MESH L=.05  N=9
++ Y.MESH L=0.3  N=14
++ Y.MESH L=2.0  N=19
++
++ REGION NUM=1 MATERIAL=1 Y.L=0.0
++ MATERIAL NUM=1 SILICON
++ MOBILITY MATERIAL=1 CONCMOD=SG FIELDMOD=SG
++
++ REGION NUM=2 MATERIAL=2 Y.H=0.0 X.L=0.7 X.H=3.7
++ MATERIAL NUM=2 OXIDE
++
++ ELEC NUM=1 X.L=3.8 X.H=4.4	Y.L=0.0 Y.H=0.0
++ ELEC NUM=2 X.L=0.7 X.H=3.7	IY.L=1  IY.H=1
++ ELEC NUM=3 X.L=0.0 X.H=0.6	Y.L=0.0 Y.H=0.0
++ ELEC NUM=4 X.L=0.0 X.H=4.4	Y.L=2.0 Y.H=2.0
++
++ DOPING UNIF P.TYPE CONC=2.5E16 X.L=0.0 X.H=4.4  Y.L=0.0 Y.H=2.0
++ DOPING UNIF P.TYPE CONC=1E16   X.L=0.0 X.H=4.4  Y.L=0.0 Y.H=0.05
++ DOPING UNIF N.TYPE CONC=1E20   X.L=0.0 X.H=1.1  Y.L=0.0 Y.H=0.2
++ DOPING UNIF N.TYPE CONC=1E20   X.L=3.3 X.H=4.4  Y.L=0.0 Y.H=0.2
++
++ MODELS CONCMOB FIELDMOB
++ METHOD AC=DIRECT ONEC
+
+.END
diff --git a/Windows/spice/examples/cider/serial/pullup.cir b/Windows/spice/examples/cider/serial/pullup.cir
new file mode 100644
index 00000000..a4d7a4d1
--- /dev/null
+++ b/Windows/spice/examples/cider/serial/pullup.cir
@@ -0,0 +1,67 @@
+BICMOS INVERTER PULLUP CIRCUIT
+
+VDD 1 0 5.0V
+VSS 2 0 0.0V
+
+VIN 3 0 0.75V
+
+VC  1 11 0.0V
+VB  5 15 0.0V
+
+Q1  11 15 4 M_NPN  AREA=4
+M1  5 3 1 1 M_PMOS W=20U L=2U AD=30P AS=30P PD=21U PS=21U
+
+CL  4 0 5.0PF
+
+.IC V(4)=0.75V V(5)=0.0V
+
+.MODEL M_PMOS PMOS VTO=-0.8 UO=250 TOX=25N NSUB=5E16
++ UCRIT=10K UEXP=.15 VMAX=50K NEFF=2 XJ=.02U
++ LD=.15U CGSO=.1N CGDO=.1N CJ=.12M MJ=0.5
++ CJSW=0.3N MJSW=0.5 LEVEL=2
+
+.MODEL M_NPN NBJT LEVEL=2
++ TITLE TWO-DIMENSIONAL NUMERICAL POLYSILICON EMITTER BIPOLAR TRANSISTOR
++ $ SINCE ONLY HALF THE DEVICE IS SIMULATED, DOUBLE THE UNIT WIDTH TO GET
++ $ 1.0 UM EMITTER.
++ OPTIONS DEFW=2.0U
++ OUTPUT STATISTICS
++ 
++ X.MESH W=2.0 H.E=0.02 H.M=0.5 R=2.0
++ X.MESH W=0.5 H.S=0.02 H.M=0.2 R=2.0
++ 
++ Y.MESH L=-0.2 N=1
++ Y.MESH L= 0.0 N=5
++ Y.MESH W=0.10 H.E=0.004 H.M=0.05  R=2.5
++ Y.MESH W=0.15 H.S=0.004 H.M=0.02  R=2.5
++ Y.MESH W=1.05 H.S=0.02  H.M=0.1   R=2.5
++
++ DOMAIN NUM=1 MATERIAL=1 X.L=2.0 Y.H=0.0
++ DOMAIN NUM=2 MATERIAL=2 X.H=2.0 Y.H=0.0
++ DOMAIN NUM=3 MATERIAL=3 Y.L=0.0
++ MATERIAL NUM=1 POLYSILICON
++ MATERIAL NUM=2 OXIDE
++ MATERIAL NUM=3 SILICON
++
++ ELEC NUM=1 X.L=0.0  X.H=0.0  Y.L=1.1  Y.H=1.3
++ ELEC NUM=2 X.L=0.0  X.H=0.5  Y.L=0.0  Y.H=0.0
++ ELEC NUM=3 X.L=2.0  X.H=3.0  Y.L=-0.2 Y.H=-0.2
++
++ DOPING GAUSS N.TYPE CONC=3E20 X.L=2.0 X.H=3.0 Y.L=-0.2 Y.H=0.0
++ + CHAR.L=0.047 LAT.ROTATE
++ DOPING GAUSS P.TYPE CONC=5E18 X.L=0.0 X.H=5.0 Y.L=-0.2 Y.H=0.0
++ + CHAR.L=0.100 LAT.ROTATE
++ DOPING GAUSS P.TYPE CONC=1E20 X.L=0.0 X.H=0.5 Y.L=-0.2 Y.H=0.0
++ + CHAR.L=0.100 LAT.ROTATE RATIO=0.7
++ DOPING UNIF  N.TYPE CONC=1E16 X.L=0.0 X.H=5.0 Y.L=0.0 Y.H=1.3
++ DOPING GAUSS N.TYPE CONC=5E19 X.L=0.0 X.H=5.0 Y.L=1.3 Y.H=1.3
++ + CHAR.L=0.100 LAT.ROTATE
++
++ METHOD AC=DIRECT ITLIM=10
++ MODELS BGN SRH AUGER CONCTAU CONCMOB FIELDMOB
+
+.TRAN 0.5NS 4.0NS
+.PRINT TRAN V(3) V(4)
+
+.OPTION ACCT BYPASS=1
+.END
diff --git a/Windows/spice/examples/cider/serial/readme b/Windows/spice/examples/cider/serial/readme
new file mode 100644
index 00000000..08f29304
--- /dev/null
+++ b/Windows/spice/examples/cider/serial/readme
@@ -0,0 +1,3 @@
+This directory contains the CIDER serial-version benchmarks used in the
+thesis "Design-Oriented Mixed-Level Circuit and Device Simulation" by
+David A. Gates.
diff --git a/Windows/spice/examples/cider/serial/recovery.cir b/Windows/spice/examples/cider/serial/recovery.cir
new file mode 100644
index 00000000..cd33be1e
--- /dev/null
+++ b/Windows/spice/examples/cider/serial/recovery.cir
@@ -0,0 +1,40 @@
+DIODE REVERSE RECOVERY
+
+VPP 1 0 0.0V (PULSE 1.0V -1.0V 1NS 1PS 1PS 20NS 40NS)
+VNN 2 0 0.0V
+RS  1 3 1.0
+LS  3 4 0.5UH
+DT  4 2 M_PIN AREA=1
+
+.MODEL M_PIN NUMD LEVEL=2
++ OPTIONS DEFW=100U
++ X.MESH N=1 L=0.0
++ X.MESH N=2 L=0.2
++ X.MESH N=4 L=0.4
++ X.MESH N=8 L=0.6
++ X.MESH N=13 L=1.0
++
++ Y.MESH N=1 L=0.0
++ Y.MESH N=9 L=4.0
++ Y.MESH N=24 L=10.0
++ Y.MESH N=29 L=15.0
++ Y.MESH N=34 L=20.0
++
++ DOMAIN NUM=1 MATERIAL=1
++ MATERIAL NUM=1 SILICON TN=20NS TP=20NS
++
++ ELECTRODE NUM=1 X.L=0.6 X.H=1.0 Y.L=0.0 Y.H=0.0
++ ELECTRODE NUM=2 X.L=-0.1 X.H=1.0 Y.L=20.0 Y.H=20.0
++
++ DOPING GAUSS P.TYPE CONC=1.0E19 CHAR.LEN=1.076 X.L=0.75 X.H=1.1 Y.H=0.0
++ + LAT.ROTATE RATIO=0.1
++ DOPING UNIF  N.TYPE CONC=1.0E14
++ DOPING GAUSS N.TYPE CONC=1.0E19 CHAR.LEN=1.614 X.L=-0.1 X.H=1.1 Y.L=20.0
++
++ MODELS BGN SRH AUGER CONCTAU CONCMOB FIELDMOB
+
+.OPTION ACCT BYPASS=1
+.TRAN 0.1NS 10NS
+.PRINT TRAN V(3) I(VIN)
+
+.END
diff --git a/Windows/spice/examples/cider/serial/rtlinv.cir b/Windows/spice/examples/cider/serial/rtlinv.cir
new file mode 100644
index 00000000..ef0dd94d
--- /dev/null
+++ b/Windows/spice/examples/cider/serial/rtlinv.cir
@@ -0,0 +1,25 @@
+RTL INVERTER
+
+VIN 1 0 DC 1 PWL 0 4 1NS 0
+VCC 12 0 DC 5.0
+RC1 12 3 2.5K
+RB1 1 2 8K
+Q1 3 2 0 QMOD AREA = 100P
+
+.OPTION ACCT BYPASS=1
+.TRAN 0.5N 5N
+.PRINT TRAN V(2) V(3)
+
+.MODEL QMOD NBJT LEVEL=1
++ X.MESH NODE=1  LOC=0.0
++ X.MESH NODE=61 LOC=3.0
++ REGION NUM=1 MATERIAL=1
++ MATERIAL NUM=1 SILICON NBGNN=1E17 NBGNP=1E17
++ MOBILITY MATERIAL=1 CONCMOD=SG FIELDMOD=SG
++ DOPING UNIF N.TYPE CONC=1E17 X.L=0.0 X.H=1.0
++ DOPING UNIF P.TYPE CONC=1E16 X.L=0.0 X.H=1.5
++ DOPING UNIF N.TYPE CONC=1E15 X.L=0.0 X.H=3.0
++ MODELS BGNW SRH CONCTAU AUGER CONCMOB FIELDMOB
++ OPTIONS BASE.LENGTH=1.0 BASE.DEPTH=1.25
+
+.END
diff --git a/Windows/spice/examples/cider/serial/vco.cir b/Windows/spice/examples/cider/serial/vco.cir
new file mode 100644
index 00000000..852ddd7f
--- /dev/null
+++ b/Windows/spice/examples/cider/serial/vco.cir
@@ -0,0 +1,41 @@
+VOLTAGE CONTROLLED OSCILLATOR
+
+RC1 7 5 1K
+RC2 7 6 1K
+
+Q5 7 7 5 QMOD AREA = 100P
+Q6 7 7 6 QMOD AREA = 100P
+
+Q3 7 5 2 QMOD AREA = 100P
+Q4 7 6 1 QMOD AREA = 100P
+
+IB1 2 0 .5MA
+IB2 1 0 .5MA
+CB1 2 0 1PF
+CB2 1 0 1PF
+
+Q1 5 1 3 QMOD AREA = 100P
+Q2 6 2 4 QMOD AREA = 100P
+
+C1 3 4 .1UF 
+
+IS1 3 0 DC 2.5MA PULSE 2.5MA 0.5MA 0 1US 1US 50MS
+IS2 4 0 1MA
+VCC 7 0 10
+
+.MODEL QMOD NBJT LEVEL=1
++ X.MESH NODE=1  LOC=0.0
++ X.MESH NODE=61 LOC=3.0
++ REGION NUM=1 MATERIAL=1
++ MATERIAL NUM=1 SILICON NBGNN=1E17 NBGNP=1E17
++ MOBILITY MATERIAL=1 CONCMOD=SG FIELDMOD=SG
++ DOPING UNIF N.TYPE CONC=1E17 X.L=0.0 X.H=1.0
++ DOPING UNIF P.TYPE CONC=1E16 X.L=0.0 X.H=1.5
++ DOPING UNIF N.TYPE CONC=1E15 X.L=0.0 X.H=3.0
++ MODELS BGNW SRH CONCTAU AUGER CONCMOB FIELDMOB
++ OPTIONS BASE.LENGTH=1.0 BASE.DEPTH=1.25
+
+.OPTION ACCT BYPASS=1 
+.TRAN 3US 600US 0 3US
+.PRINT TRAN V(4)
+.END