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| author | rahulp13 | 2020-02-28 11:38:58 +0530 |
|---|---|---|
| committer | rahulp13 | 2020-02-28 11:38:58 +0530 |
| commit | 246319682f60293b132fca1ce6e24689c6682617 (patch) | |
| tree | 6871b758a17869efecfd617f5513e31f9a933f4a /Windows/spice/examples/TransmissionLines/ltra2_2_line.sp | |
| parent | d9ab84106cac311d953f344386fef1c1e2bca1cf (diff) | |
| download | eSim-246319682f60293b132fca1ce6e24689c6682617.tar.gz eSim-246319682f60293b132fca1ce6e24689c6682617.tar.bz2 eSim-246319682f60293b132fca1ce6e24689c6682617.zip | |
initial commit
Diffstat (limited to 'Windows/spice/examples/TransmissionLines/ltra2_2_line.sp')
| -rw-r--r-- | Windows/spice/examples/TransmissionLines/ltra2_2_line.sp | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/Windows/spice/examples/TransmissionLines/ltra2_2_line.sp b/Windows/spice/examples/TransmissionLines/ltra2_2_line.sp new file mode 100644 index 00000000..2a4ceaa7 --- /dev/null +++ b/Windows/spice/examples/TransmissionLines/ltra2_2_line.sp @@ -0,0 +1,24 @@ +MOSdriver -- 2 lossy lines LTRA model -- C load +m5 0 168 2 0 mn0p9 w = 18.0u l=0.9u +m6 1 168 2 1 mp1p0 w = 36.0u l=1.0u +m1 0 3 4 0 mn0p9 w = 18.0u l=0.9u +m2 1 3 4 1 mp1p0 w = 36.0u l=1.0u +CN2 2 0 0.025398e-12 +CN3 3 0 0.007398e-12 +CN4 4 0 0.025398e-12 +CN5 5 0 0.007398e-12 +o1 2 0 3 0 lline +o2 4 0 5 0 lline +vdd 1 0 dc 5.0 +VS 168 0 PULSE (0 5 15.9NS 0.2NS 0.2NS 15.8NS 32NS ) +.control +TRAN 0.2N 47N 0 0.1N +plot v(2) v(3) v(4) v(5) +.endc +.MODEL mn0p9 NMOS VTO=0.8 KP=48U GAMMA=0.30 PHI=0.55 ++LAMBDA=0.00 CGSO=0 CGDO=0 CJ=0 CJSW=0 TOX=18000N LD=0.0U +.MODEL mp1p0 PMOS VTO=-0.8 KP=21U GAMMA=0.45 PHI=0.61 ++LAMBDA=0.00 CGSO=0 CGDO=0 CJ=0 CJSW=0 TOX=18000N LD=0.0U +.model lline ltra rel=1 r=12.45 g=0 l=8.972e-9 c=0.468e-12 ++len=16 steplimit compactrel=1.0e-3 compactabs=1.0e-14 +.end |