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+DEVICES
+=======
+
+Table of contents
+
+1. Introduction
+2. Linear Devices
+ 2.1 CAP - Linear capacitor
+ 2.2 IND - Linear inductor
+ 2.3 RES - Linear resistor
+3. Distributed Elements
+ 3.1 CPL - Simple Coupled Multiconductor Lines (Kspice)
+ 3.2 LTRA - Lossy Transmission line
+ 3.3 TRA  - Transmission line
+ 3.4 TXL - Simple Lossy Transmission Line (Kspice)
+ 3.5 URC - Uniform distributed RC line
+4. Voltage and current sources
+ 4.1 ASRC - Arbitrary Source
+ 4.2 CCCS - Current Controlled Current Source
+ 4.3 CCVS - Current Controlled Voltage Source
+ 4.4 ISRC - Independent Current Source
+ 4.5 VCCS - Voltage Controlled Current Source
+ 4.6 VCVS - Voltage Controlled Voltage Source
+ 4.7 VSRC - Independent Voltage Source
+5. Switches
+ 5.1 CSW - Current controlled switch
+ 5.2 SW - Voltage controlled switch
+6. Diodes
+ 6.1 DIO - Junction Diode
+7. Bipolar devices
+ 7.1 BJT - Bipolar Junction Transistor
+ 7.2 BJT2 - Bipolar Junction Transistor
+ 7.3 VBIC - Bipolar Junction Transistor
+8. FET devices
+ 8.1 JFET - Junction Field Effect transistor
+9. HFET Devices
+ 9.1 HFET1 - Heterostructure Field Effect Transistor Level 1
+ 9.2 HFET2 - Heterostructure Field Effect Transistor Level 2
+10. MES devices
+ 10.1 MES - MESFET model
+ 10.2 MESA - MESFET model (MacSpice3f4)
+11. MOS devices
+ 11.1 MOS1 - Level 1 MOS model
+ 11.2 MOS2 - Level 2 MOS model
+ 11.3 MOS3 - Level 3 MOS model
+ 11.4 MOS6 - Level 6 MOS model
+ 11.5 MOS9 - Level 9 MOS model
+ 11.6 BSIM1 - BSIM model level 1
+ 11.7 BSIM2 - BSIM model level 2
+ 11.8 BSIM3 - BSIM model level 3 vers. 0
+ 11.9 BSIM3 - BSIM model level 3 vers. 1
+ 11.10 BSIM3 - BSIM model level 3 vers. 2
+ 11.11 BSIM3 - BSIM model level 3 vers. 3
+ 11.12 BSIM4 - BSIM model level 4
+ 11.13 HiSIM2 - Hiroshima-University STARC IGFET Model
+ 11.14 HiSIM_HV - Hiroshima-University STARC IGFET High Voltage Model
+12. SOI devices
+ 12.1 BSIM3SOI_FD - SOI model (fully depleted devices)
+ 12.2 BSIM3SOI_DD - SOI Model (dynamic depletion model)
+ 12.3 BSIM3SOI_PD - SOI model (partially depleted devices)
+ 12.4 BSIMSOI - SOI model (partially/full depleted devices)
+ 12.5 SOI3 - STAG SOI3 Model
+13. Verilog-A models
+ 13.1 EKV MOS model
+ 13.2 PSP MOS model
+ 13.3 HICUM0 Bipolar Model
+ 13.4 HICUM2 Bipolar Model
+ 13.5 Mextram Bipolar Model
+14. XSPICE code models
+
+                             ------------------
+
+1. Introduction
+
+This file contains the status of devices available in ngspice. This file
+will be updated every time the device specific code is altered or changed to reflect the current status of this important part of the simulator
+
+
+2. Linear Devices
+
+
+ 2.1 CAP - Linear capacitor
+
+     Ver:    N/A
+     Class:  C
+     Level:  1 (and only)
+     Dir:    devices/cap
+     Status:
+
+     Enhancements over the original model:
+      - Parallel Multiplier
+      - Temperature difference from circuit temperature
+      - Preliminary technology scaling support
+      - Model capacitance
+      - Cj calculation based on relative dielectric constant
+        and insulator thickness
+
+
+ 2.2 IND - Linear Inductor
+
+     Ver:    N/A
+     Class:  L
+     Level:  1 (and only)
+     Dir:    devices/ind
+     Status:
+
+     Enhancements over the original model:
+      - Parallel Multiplier
+      - Temperature difference from circuit temperature
+      - Preliminary technology scaling support
+      - Model inductance
+      - Inductance calculation for toroids or solenoids
+        on the model line.
+
+ 2.3 RES - Linear resistor
+
+     Ver:    N/A
+     Class:  R
+     Level:  1 (and only)
+     Dir:    devices/res
+     Status:
+
+     Enhancements over the original model:
+      - Parallel Multiplier
+      - Different value for ac analysis
+      - Temperature difference from circuit temperature
+      - Noiseless resistor
+      - Flicker noise
+      - Preliminary technology scaling support
+
+
+3. Distributed elements
+
+
+ 3.1 CPL - Simple Coupled Multiconductor Lines (Kspice)
+
+     Ver:    N/A
+     Class:  P
+     Level:  1 (and only)
+     Dir:    devices/cpl
+     Status:
+
+     This model comes from swec and kspice. It is not documented, if
+     you have kspice docs, can you write a short description
+     of its use ?
+
+     - Does not implement parallel code switches
+     - Probably a lot of memory leaks
+
+     Enhancements over the original model:
+
+     - Better integrated into ngspice adding CPLask, CPLmAsk and
+       CPLunsetup functions
+
+ 3.2 LTRA - Lossy Transmission line
+
+     Ver:    N/A
+     Class:  O
+     Level:  1 (and only)
+     Dir:    devices/ltra
+     Status:
+
+     - Original spice model.
+     - Does not implement parallel code switches.
+
+ 3.3 TRA  - Transmission line
+
+     Ver:    N/A
+     Class:  T
+     Level:  1 (and only)
+     Dir:    devices/tra
+     Status:
+
+    - Original spice model.
+    - Does not implement parallel code switches.
+
+ 3.4 TXL - Simple Lossy Transmission Line (Kspice)
+
+     Ver:    N/A
+     Class:  Y
+     Level:  1 (and only)
+     Dir:    devices/txl
+     Status:
+
+     This model comes from kspice. It is not documented, if
+     you have kspice docs, can you write a short description
+     of its use ?
+
+     There is some code left out from compilation:
+     TXLaccept and TXLfindBr. Any ideas ?
+
+     - Does not implement parallel code switches
+
+
+ 3.5 URC - Uniform distributed RC line
+
+     Ver:    N/A
+     Class:  U
+     Level:  1 (and only)
+     Dir:    devices/urc
+     Status:
+
+     - Original spice model.
+     - Does not implement parallel code switches.
+
+
+4. Voltage and current sources
+
+ 4.1 ASRC - Arbitrary Source
+
+     Ver:    N/A
+     Class:  B
+     Level:  1 (and only)
+     Dir:    devices/asrc
+     Status:
+
+     The arbitrary source code has been corrected with the patch
+     available on the Internet. There is still an issue to fix, the
+     current of current-controlled generators.
+
+ 4.2 CCCS - Current Controlled Current Source
+
+      Ver:    N/A
+      Class:  F
+      Level:  1 (and only)
+      Dir:    devices/cccs
+      Status:
+
+      - Original spice model.
+
+ 4.3 CCVS - Current Controlled Voltage Source
+
+     Ver:    N/A
+     Class:  H
+     Level:  1 (and only)
+     Dir:    devices/ccvs
+     Status:
+
+     - Original spice model.
+
+
+ 4.4 ISRC - Independent Current Source
+
+     Ver:    N/A
+     Class:  I
+     Level:  1 (and only)
+     Dir:    devices/isrc
+     Status:
+
+     This is the original spice device improved by Alan Gillespie
+     with the following features:
+
+     - Source ramping
+     - Check for non-monotonic series in PWL
+
+
+ 4.5 VCCS - Voltage Controlled Current Source
+
+     Ver:    N/A
+     Class:  G
+     Level:  1 (and only)
+     Dir:    devices/vccs
+     Status:
+
+     - Original spice model.
+
+
+4.6 VCVS - Voltage Controlled Voltage Source
+
+    Ver:    N/A
+    Class:  E
+    Level:  1 (and only)
+    Dir:    devices/vcvs
+    Status:
+
+    - Original spice model.
+
+ 4.7 VSRC - Independent Voltage Source
+
+     Ver:    N/A
+     Class:  V
+     Level:  1 (and only)
+     Dir:    devices/vsrc
+     Status:
+
+     This is the original spice device improved by Alan Gillespie
+     with the following features:
+
+     - Source ramping
+     - Check for non-monotonic series in PWL
+
+
+5. Switches
+
+ 5.1 CSW - Current controlled switch
+
+      Ver:    N/A
+      Class:  W
+      Level:  1 (and only)
+      Dir:    devices/csw
+      Status:
+
+      - This model comes from Jon Engelbert.
+
+
+ 5.2 SW - Voltage controlled switch
+
+     Ver:    N/A
+     Class:  S
+     Level:  1 (and only)
+     Dir:    devices/sw
+     Status:
+
+     - This model comes from Jon Engelbert.
+
+
+6. Diodes
+
+ 6.1 DIO - Junction Diode
+
+     Ver:    N/A
+     Class:  D
+     Level:  1 (and only)
+     Dir:    devices/dio
+     Status:
+
+     Enhancements over the original model:
+     - Parallel Multiplier
+     - Temperature difference from circuit temperature
+     - Forward and reverse knee currents
+     - Periphery (sidewall) effects
+     - Temperature correction of some parameters
+
+
+7. Bipolar devices
+
+ 7.1 BJT - Bipolar Junction Transistor
+
+     Ver:    N/A
+     Class:  Q
+     Level:  1
+     Dir:    devices/bjt
+     Status:
+
+     Enhancements over the original model:
+     - Parallel Multiplier
+     - Temperature difference from circuit temperature
+     - Different area parameters for collector, base and emitter
+
+ 7.2 BJT2 - Bipolar Junction Transistor
+
+     Ver:    N/A
+     Class:  Q
+     Level:  2
+     Dir:    devices/bjt2
+     Status:
+
+     This is the BJT model written by Alan Gillespie to support lateral
+     devices. The model has been hacked by Dietmar Warning fixing some bugs
+     and adding some features (temp. dependency on resistors).
+
+     Enhancements over the original model:
+     - Parallel Multiplier
+     - Temperature dependency on rc,rb,re
+     - Temperature difference from circuit temperature
+     - Different area parameters for collector, base and emitter
+
+ 7.3 VBIC - Bipolar Junction Transistor
+
+     Ver:    N/A
+     Class:  Q
+     Level:  4 & 9
+     Dir:    devices/vbic
+     Status:
+
+     This is the Vertical Bipolar InterCompany model in version 1.2. The author
+     of VBIC is Colin McAndrew mcandrew@ieee.org.
+     Spice3 Implementation: Dietmar Warning DAnalyse GmbH
+     Web Site: http://www.designers-guide.com/VBIC/index.html
+
+     Notes: This is the 4 terminals model, without excess phase and thermal
+            network.
+
+
+8. FET devices
+
+ 8.1 JFET - Junction Field Effect transistor
+
+     Ver:    N/A
+     Class:  J
+     Level:  1
+     Dir:    devices/jfet
+     Status:
+
+     This is the original spice JFET model.
+
+     Enhancements over the original model:
+     - Alan Gillespie's modified diode model
+     - Parallel multiplier
+     - Instance temperature as difference for circuit temperature
+
+ 8.2 JFET2 - Junction Field Effect Transistor  (PS model)
+
+     Ver:    N/A
+     Class:  J
+     Level:  2
+     Dir:    devices/jfet2
+     Status:
+
+     This is the Parker Skellern model for MESFETs.
+
+     Web Site: http://www.elec.mq.edu.au/cnerf/psmodel.htm
+
+     Enhancements over the original model:
+     - Parallel multiplier
+     - Instance temperature as difference for circuit temperature
+
+
+9. HFET Devices
+
+   Added code from macspice3f4 HFET1&2 and MESA model
+   Original note:
+     Added device calls for Mesfet models and HFET models
+     provided by Trond Ytterdal as of Nov 98
+
+ 9.1 HFET1 - Heterostructure Field Effect Transistor Level 1
+
+     Ver:    N/A
+     Class:  Z
+     Level:  5
+     Dir:    devices/hfet1
+     Status:
+
+     This is the Heterostructure Field Effect Transistor model from:
+     K. Lee, M. Shur, T. A. Fjeldly and T. Ytterdal
+     "Semiconductor Device Modeling in VLSI",
+     1993, Prentice Hall, New Jersey
+
+     Enhancements over the original model:
+     - Parallel multiplier
+     - Instance temperature as difference for circuit temperature
+     - Added pole-zero analysis
+
+
+ 9.2 HFET2 - Heterostructure Field Effect Transistor Level 2
+
+     Ver:    N/A
+     Class:  Z
+     Level:  6
+     Dir:    devices/hfet2
+     Status:
+
+     Simplified version of hfet1
+
+     Enhancements over the original model:
+     - Parallel multiplier
+     - Instance temperature as difference for circuit temperature
+     - Added pole-zero analysis
+
+
+10. MES devices
+
+ 10.1 MES - MESFET model
+
+      Ver:    N/A
+      Class:  Z
+      Level:  1
+      Dir:    devices/mes
+      Status:
+
+      This is the original spice3 MESFET model (Statz).
+
+      Enhancements over the original model:
+      - Parallel multiplier
+      - Alan Gillespie junction diodes implementation
+
+
+  Added code from macspice3f4 HFET1&2 and MESA model
+  Original note:
+  Added device calls for Mesfet models and HFET models
+  provided by Trond Ytterdal as of Nov 98
+
+10.2 MESA - MESFET model (MacSpice3f4)
+
+     Ver:    N/A
+     Class:  Z
+     Level:  2,3,4
+     Dir:    devices/mesa
+     Status:
+
+     This is a multilevel model. It contains code for mesa levels
+     2,3 and 4
+
+     Enhancements over the original model:
+     - Parallel multiplier
+     - Instance temperature as difference from circuit temperature
+     - Added pole-zero analysis
+
+
+
+11. MOS devices
+
+ 11.1 MOS1 - Level 1 MOS model
+
+      Ver:    N/A
+      Class:  M
+      Level:  1
+      Dir:    devices/mos1
+      Status:
+
+      This is the so-called Schichman-Hodges model.
+
+      Enhancements over the original model:
+      - Parallel multiplier
+      - Temperature difference from circuit temperature
+
+ 11.2 MOS2 - Level 2 MOS model
+
+      Ver:    N/A
+      Class:  M
+      Level:  2
+      Dir:    devices/mos2
+      Status:
+
+      This is the so-called  Grove-Frohman model.
+
+      Enhancements over the original model:
+      - Parallel multiplier
+      - Temperature difference from circuit temperature
+
+
+ 11.3 MOS3 - Level 3 MOS model
+
+      Ver:    N/A
+      Class:  M
+      Level:  3
+      Dir:    devices/mos3
+      Status:
+
+      Enhancements over the original model:
+      - Parallel multiplier
+      - Temperature difference from circuit temperature
+
+
+ 11.4 MOS6 - Level 6 MOS model
+
+      Ver:    N/A
+      Class:  M
+      Level:  6
+      Dir:    devices/mos6
+      Status:
+
+      Enhancements over the original model:
+      - Parallel multiplier
+      - Temperature difference from circuit temperature
+
+
+ 11.5 MOS9 - Level 9 MOS model
+
+      Ver:    N/A
+      Class:  M
+      Level:  9
+      Dir:    devices/mos9
+      Status:
+
+      This is a slightly modified Level 3 MOSFET model.
+      (Whatever the implementer have had in mind.)
+      Not to confuse with Philips level 9.
+      Enhancements over the original model:
+      - Temperature difference from circuit temperature
+
+
+ 11.6 BSIM1 - BSIM model level 1
+
+      Ver:    N/A
+      Class:  M
+      Level:  4
+      Dir:    devices/bsim1
+      Status:
+
+      Enhancements over the original model:
+      - Parallel multiplier
+      - Noise analysis
+
+      BUGS:
+      Distortion analysis probably does not
+      work with "parallel" devices. Equations
+      are too intricate to deal with. Any one
+      has ideas on the subject ?
+
+
+ 11.7 BSIM2 - BSIM model level 2
+
+      Ver:    N/A
+      Class:  M
+      Level:  5
+      Dir:    devices/bsim2
+      Status:
+
+      Enhancements over the original model:
+      - Parallel multiplier
+      - Noise analysis
+
+
+ 11.8 BSIM3v0 - BSIM model level 3
+
+      Ver:    3.0
+      Class:  M
+      Level:  8 & 49, version = 3.0
+      Dir:    devices/bsim3v0
+      Status: TO BE TESTED AND IMPROVED
+
+
+ 11.9 BSIM3v1 - BSIM model level 3
+
+      Ver:    3.1
+      Class:  M
+      Level:  8 & 49, version = 3.1
+      Dir:    devices/bsim3v1
+      Status: TO BE TESTED AND IMPROVED
+
+       This is the BSIM3v3.1 model modified by Serban Popescu.
+       This is level 49 model. It is an implementation that supports
+       "HDIF" and "M" parameters.
+
+
+ 11.10 BSIM3 - BSIM model level 3
+
+       Ver:    3.2.4
+       Class:  M
+       Level:  8 & 49, version = 3.2.2, 3.2.3, 3.2.4
+       Dir:    devices/bsim3v32 (level 3.2.4)
+       Status: o.k.
+
+       This is another BSIM3 model from Berkeley Device Group.
+       You can find some test netlists with results for this model
+       on its web site.
+
+       Web site: http://www-device.eecs.berkeley.edu/~bsim3
+
+       Enhancements over the original model:
+        - Parallel Multiplier
+        - delvto, mulu0 instance parameter
+        - ACM Area Calculation Method
+        - Multirevision code (supports all 3v3.2 minor revisions)
+        - NodesetFix
+
+
+ 11.11 BSIM3 - BSIM model level 3
+
+       Ver:    3.3.0
+       Class:  M
+       Level:  8 & 49, version = 3.3.0
+       Dir:    devices/bsim3 (level 3.3.0)
+       Status: o.k.
+
+       This is the actual BSIM3 model from Berkeley Device Group.
+       You can find some test netlists with results for this model
+       on its web site.
+
+       Web site: http://www-device.eecs.berkeley.edu/~bsim3
+
+       Enhancements over the original model:
+        - Parallel Multiplier
+        - ACM Area Calculation Method
+        - Multirevision code (supports all 3v3.2 minor revisions)
+        - NodesetFix
+        - Support for Multi-core processors using OpenMP
+
+
+ 11.12 BSIM4 - BSIM model level 4
+
+       Ver:    4.2.0 - 4.6.5
+       Class:  M
+       Level:  14 & 54, version = 4.0, 4.1, 4.2, 4.3, 4.4, 4.5, 4.6
+       Dir:    devices/bsim4 (level 4.6.5)
+       Status: o.k.
+
+       This is the actual BSIM4 model from Berkeley Device Group.
+       Test are available on its web site.
+
+       Web site: http://www-device.eecs.berkeley.edu/~bsim3/bsim4.html
+
+       Enhancements over the original model:
+        - Parallel Multiplier
+        - NodesetFix
+        - Support for Multi-core processors using OpenMP
+
+
+ 11.13 HiSIM2 - Hiroshima-university STARC IGFET Model
+
+       Ver:    2.7.0
+       Class:  M
+       Level:  61, 68
+       Dir:    devices/hisim2
+       Status: TO BE TESTED.
+
+       This is the HiSIM2 model available from Hiroshima University
+       (Ultra-Small Device Engineering Laboratory)
+
+       Web site: http://home.hiroshima-u.ac.jp/usdl/HiSIM.html
+
+
+ 11.14 HiSIM_HV - Hiroshima-University STARC IGFET High Voltage Model
+
+       Ver:    1.2.3
+       Class:  M
+       Level:  62, 73
+       Dir:    devices/hisimhv
+       Status: TO BE TESTED.
+
+       This is the HiSIM_HV model available from Hiroshima University
+       (Ultra-Small Device Engineering Laboratory)
+
+       Web site: http://home.hiroshima-u.ac.jp/usdl/HiSIM.html
+
+
+12. SOI devices
+
+ 12.1 BSIM3SOI_FD - SOI model (fully depleted devices)
+
+      Ver:    2.1
+      Class:  M
+      Level:  55
+      Dir:    devices/bsim3soi_fd
+      Status: TO BE TESTED.
+
+      FD model has been integrated.
+      There is a bsim3soifd directory under the test
+      hierarchy. Test circuits come from the bsim3soi
+
+      Web site at: http://www-device.eecs.berkeley.edu/~bsimsoi
+
+
+
+ 12.2 BSIM3SOI_DD - SOI Model (dynamic depletion model)
+
+      Ver:    2.1
+      Class:  M
+      Level:  56
+      Dir:    devices/bsim3soi_dd
+      Status: TO BE TESTED.
+
+      There is a bsim3soidd directory under the
+      test hierarchy. Test circuits come from bsim3soi
+
+      Web site at: http://www-device.eecs.berkeley.edu/~bsimsoi
+
+
+
+ 12.3 BSIM3SOI_PD - SOI model (partially depleted devices)
+
+      Ver:    2.2.1
+      Class:  M
+      Level:  57
+      Dir:    devices/bsim3soi_pd
+      Status: TO BE TESTED.
+
+      PD model has been integrated. There is a bsim3soipd directory
+      under the test hierarchy. Test circuits come from the bsim3soi
+
+      Web site at: http://www-device.eecs.berkeley.edu/~bsimsoi
+
+
+
+ 12.4 BSIMSOI - Berkeley SOI model (partially/full depleted devices)
+
+      Ver:    4.3.1
+      Class:  M
+      Level:  10 & 58
+      Dir:    devices/bsim3soi
+      Status: o.k.
+
+      This is the actual version from Berkeley. This version is
+      backward compatible with its previous versions BSIMSOI3.x.
+      Usable for partially/full depleted devices.
+
+      Web site at: http://www-device.eecs.berkeley.edu/~bsimsoi
+
+       Enhancements over the original model:
+       - Parallel Multiplier
+           - Support for Multi-core processors using OpenMP
+
+
+
+ 12.5 SOI3 - STAG SOI3 Model
+
+      Ver:    2.6
+      Class:  M
+      Level:  61
+      Dir:    devices/soi3
+      Status: OBSOLETE
+
+
+
+13. Verilog-A models
+
+      Configuring ngspice with ADMS (see Readme.adms) following
+      devices are available:
+
+ 13.1 EKV MOS Model
+
+      Ver:    2.6
+      Level:  44
+      Dir:    devices/adms/ekv
+      Status: TO BE TESTED
+
+      EKV version based on a contribution of Ivan Riis Nielsen 11/2006
+
+      Web site at: http://legwww.epfl.ch/ekv/
+      (but EPFL is not publishing any usefull code)
+
+
+ 13.2 PSP MOS Model
+
+      Ver:    102.1
+      Level:  45
+      Dir:    devices/adms/psp102
+      Status: TO BE TESTED
+
+      Philips SimKit 2.5.
+
+
+ 13.3 HICUM0 Bipolar Model
+
+      Ver:    Level_0 Version_1.12
+      Level:  7
+      Dir:    devices/adms/hicum0
+      Status: TO BE TESTED
+
+      A simplified version of HICUM Level2 model for BJT
+      Web site at: http://www.iee.et.tu-dresden.de/iee/eb/hic_new
+
+
+ 13.4 HICUM2 Bipolar Model
+
+      Ver:    Level_2 Version_2.22
+      Level:  8
+      Dir:    devices/adms/hicum2
+      Status: TO BE TESTED
+
+      Web site at: http://www.iee.et.tu-dresden.de/iee/eb/hic_new/hic_start.html
+
+
+ 13.5 Mextram Bipolar Model
+
+      Ver:    504.6.1
+      Level:  6
+      Dir:    devices/adms/mextram
+      Status: TO BE TESTED
+
+      Web site at: http://mextram.ewi.tudelft.nl/ and http://mextram.sourceforge.net/
+
+ 14. XSpice code models, see ngspice manual chapt. 12