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| author | Aditya Minocha | 2024-08-25 21:38:12 +0530 |
|---|---|---|
| committer | GitHub | 2024-08-25 21:38:12 +0530 |
| commit | 0cc5a5f7833aa0fc6aa88bddaec4771d95cf4bad (patch) | |
| tree | aadde3f4dcef4aff01f7a7ad1b8308f495387c8f /SN54HC148/OR.sub | |
| parent | 55568c864d1f19971c15c27df999ea161a07f366 (diff) | |
| download | eSim-0cc5a5f7833aa0fc6aa88bddaec4771d95cf4bad.tar.gz eSim-0cc5a5f7833aa0fc6aa88bddaec4771d95cf4bad.tar.bz2 eSim-0cc5a5f7833aa0fc6aa88bddaec4771d95cf4bad.zip | |
SN54HC148 IC- 8:3 Priority Encoder
Diffstat (limited to 'SN54HC148/OR.sub')
| -rw-r--r-- | SN54HC148/OR.sub | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/SN54HC148/OR.sub b/SN54HC148/OR.sub new file mode 100644 index 00000000..f5a8f127 --- /dev/null +++ b/SN54HC148/OR.sub @@ -0,0 +1,14 @@ +* Subcircuit OR
+.subckt OR net-_m1-pad2_ net-_m3-pad2_ net-_m5-pad1_ net-_m2-pad1_ net-_m1-pad3_
+* c:\fossee\esim\library\subcircuitlibrary\or\or.cir
+.include NMOS-180nm.lib
+.include PMOS-180nm.lib
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m4 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m5 net-_m5-pad1_ net-_m1-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m3 net-_m2-pad3_ net-_m3-pad2_ net-_m1-pad1_ net-_m2-pad3_ CMOSP W=100u L=100u M=1
+m2 net-_m2-pad1_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad1_ CMOSP W=100u L=100u M=1
+m6 net-_m2-pad1_ net-_m1-pad1_ net-_m5-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1
+* Control Statements
+
+.ends OR
\ No newline at end of file |